2.2 PF

SHDN

GND

IN

OUT

FAULT

100

k

Ÿ

2.2 PF

CERAMIC

VIN

VO

CC

33 nF

11

LP3982

www.ti.com

SNVS185F – FEBRUARY 2002 – REVISED APRIL 2017

Product Folder Links: LP3982

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Copyright © 2002–2017, Texas Instruments Incorporated

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LP3982 can provide 300-mA output current with 2.5-V to 6-V input. It is stable with a 2.2-μF ceramic output

capacitor. An optional external bypass capacitor reduces the output noise without slowing down the load

transient response. Typical output noise is 37 μVRMS at frequencies from 10 Hz to 100 kHz. Typical PSSR is

60 dB at 1 kHz.

8.2 Typical Application

Figure 14. LP3982 Typical Application (Fixed VOUT Version)

8.2.1 Design Requirements

For typical ultra low-dropout CMOS-regulator applications, use the parameters listed in Table 1.

Table 1. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

Minimum input voltage

VOUT + 0.5 V

Nominal output voltage

3.3 V

Maximum output current

300 mA

RMS noise, 10 Hz to 100 kHz

37 µVRMS

PSRR at 1 kHz

60 dB

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LP3982 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.