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OPA698 Datasheet(PDF) 28 Page - Texas Instruments

Part # OPA698
Description  UNITY-GAIN STABLE WIDEBAND VOLTAGE LIMITING AMPLIFIER
PDF  34 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

OPA698 Datasheet(HTML) 28 Page - Texas Instruments

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E
N +
E
NI
2
) IBNRS
2
) 4kTRS )
I
BI
R
F
NG
2
)
4kTR
F
NG
(6)
DC Accuracy and Offset Control
OPA698M
SGLS287A – MAY 2005 – REVISED MARCH 2006
Evaluating these two equations for the OPA698 circuit and component values (see Figure 47) gives a total output
spot noise voltage of 11.9 nV/
√Hz and a total equivalent input spot noise voltage of 6 nV/√Hz. This total
input-referred spot noise voltage is only slightly higher than the 5.6 nV/
√Hz specification for the op amp voltage
noise alone. This is the case as long as the impedances appearing at each op amp input is limited to a maximum
value of 300
Ω. Keeping both (R
F || RG) and the noninverting input source impedance less than 300 Ω satisfies
both noise and frequency response flatness considerations. Since the resistor-induced noise is relatively
negligible, additional capacitive decoupling across the bias current cancellation resistor (RT) for the inverting op
amp configuration of Figure 49 is not required, but is still desirable.
The balanced input stage of a wideband voltage feedback op amp allows good output dc accuracy in a large
variety of applications. The power-supply current trim for the OPA698 gives even tighter control than comparable
products. Although the high-speed input stage does require relatively high input bias current (typically ±8 µA at
each input terminal), the close matching between them may be used to reduce the output dc error caused by this
current. The total output offset voltage may be considerably reduced by matching the dc source resistances
appearing at the two inputs. This reduces the output dc error due to the input bias currents to the offset current
times the feedback resistor. Evaluating the configuration of Figure 47, using a worst-case +25°C input offset
voltage and current specifications, gives a worst-case output offset voltage equal to:
– (NG = noninverting signal gain)
± (NG × V
IO(MAX)) ± [RF x IIO(MAX)]
= ±(2 × 8 mV) ± (402
Ω × 3 µA)
= ±17.2 mV
A fine-scale output offset null or dc operating point adjustment is often required. Numerous techniques are
available for introducing dc offset control into an op amp circuit. Most of these techniques eventually reduce to
adding a dc current through the feedback resistor. In selecting an offset trim method, one key consideration is
the impact on the desired signal path frequency response. If the signal path is intended to be noninverting, the
offset control is best applied as an inverting summing signal to avoid interaction with the signal source. If the
signal path is intended to be inverting, applying the offset control to the noninverting input may be considered.
However, the dc offset voltage on the summing junction sets up a dc current back into the source which must be
considered. Applying an offset adjustment to the inverting op amp input can change the noise gain and
frequency response flatness. For a dc-coupled inverting amplifier, Figure 71 shows one example of an offset
adjustment technique that has minimal impact on the signal frequency response. In this case, the dc offsetting
current is brought into the inverting input node through resistor values that are much larger than the signal path
resistors. This insures that the adjustment circuit has minimal effect on the loop gain as well as the frequency
response.
28
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