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OPA698M

SGLS287A – MAY 2005 – REVISED MARCH 2006

ELECTRICAL CHARACTERISTICS (continued)

V

S = ±5 V, VICM = 0 V, RL = 500 Ω, limiter pins open (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DC PERFORMANCE

TA = 25°C

52

58

Open-loop voltage gain (AVOL)

VO = ±0.5 V

dB

TA = Full range

43

TA = 25°C

±2

±8

Input offset voltage (VIO)

mV

TA = Full range

±12

TA = 25°C

±3

±10

Input bias current (IIB)(2)

µA

TA = Full range

±18

TA = 25°C

±0.3

±3

Input offset current (IIO)

µA

TA = Full range

±4

INPUT

TA = 25°C

52

58

Common-mode rejection ratio (CMRR)

VICM = ±0.5 V, Input referred

dB

TA = Full range

47

TA = 25°C

±3.2

±3.3

M

Ω

Common-mode input voltage range (VICR)(3)

pF

TA = Full range

±3.1

0.32

M

Ω

Input impedance, differential mode

1

pF

3.5

M

Ω

Input impedance, common mode

1

pF

OUTPUT

TA = 25°C

±3.9

±4

VH = 4.3 V, VL = –4.3 V,

Output voltage range (VOH, VOL)

V

RL≥ 500 Ω

TA = Full range

±3.7

TA = 25°C

110

165

VH = 4.3 V, VL = –4.3 V,

Current output, sourcing (IOH)

mA

RL = 20 Ω

TA = Full range

100

TA = 25°C

–90

–130

VH = 4.3 V, VL = –4.3 V,

Current output, sinking (IOL)

mA

RL = 20 Ω

TA = Full range

–80

Closed-loop output impedance

G = +1, RF = 25 Ω, f < 100 kHz

0.2

Ω

POWER SUPPLY

Operating voltage (VS)

±5

±6

V

TA = 25°C

15

15.5

16

Quiescent current (IS)

mA

TA = Full range

13.5

18

TA = 25°C

65

76

dB

Input referred,

Power supply rejection ratio (PSRR)

VS = ±4.5 V to ±5.5 V

TA = Full range

60

dB

OUTPUT VOLTAGE LIMITERS (pins 5 and 8)

TA = 25°C

±3.3

±3.6

Default output limited voltage

Limiter pins open

V

TA = Full range

±3

Limiter output offset voltage

(VO – VH) or (VO – VL)

TA = Full range

±15

±50

mV

TA = 25°C

40

55

65

Limiter input bias current magnitude(4)

VO = 0 V

µA

TA = Full range

35

70

3.4

M

Ω

Limiter input impedance

1

pF

Limiter feedthrough(5)

f = 5 MHz

–68

dB

Maximum limiter voltage

±4.3

V

Minimum limiter voltage separation

400

mV

Op amp bias current shift (2)

3

µA

(2)

Current is considered positive out of node.

(3)

CMIR tested as < 3-dB degradation from minimum CMRR at specified limits.

(4)

IVH (VH bias current) is positive and IVL (VL bias current) is negative under these conditions. See Note 2, Figure 47 and Figure 66.

(5)

Limiter feedthrough is the ratio of the output magnitude to the sine wave added to VH (or VL) when VIN = 0.

3

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