PLL1707

PLL1708

SLES065 – DECEMBER 2002

www.ti.com

16

Configuration Register

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

1

1

0

1

1

RSV

RSV

RSV

RSV

RSV

CFG1

RSV

RSV

RSV

RSV

Table 7. Configuration Register Mapping

REGISTER

BIT NAME

DESCRIPTION

Configuration

RSV

Reserved, must be 0

Configuration

CFG1

SCKO1 configuration

CFG1: SCKO1 Configuration Control

CFG1

CONFIGURATION 1

0

36.864 MHz, 24.576 MHz for SCKO1 (default)

1

18.432 MHz, 12.288 MHz for SCKO1

The system clock SCKO1 frequency can be selected by CSEL (pin 12) and CFG1 (register).

CFG1

(REGISTER)

CSEL

(PIN 12)

SCKO1

0

LOW

36.864 MHz

0

HIGH

24.576 MHz

1

LOW

18.432 MHz

1

HIGH

12.288 MHz

CONNECTION DIAGRAM

Figure 15 shows the typical connection circuit for the PLL1707. There are four grounds for digital and analog power

supplies. However, the use of one common ground connection is recommended to avoid latch-up or other

power-supply-related troubles. Power supplies should be bypassed as close as possible to the device.

MPEG-2 APPLICATIONS

Typical applications for the PLL1707/8 are MPEG-2 based systems such as DVD recorders, HDD recorders, DVD players,

DVD add-on cards for multimedia PCs, digital HDTV systems, and set-top boxes. The PLL1707/8 provides audio system

clocks for a CD-DA DSP, DVD DSP, Karaoke DSP, ADC(s), and DAC(s) from a 27-MHz video clock.