PLL1707

PLL1708

SLES065 – DECEMBER 2002

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17

SR(MS)

FS1 (MD)

16

15

14

13

12

11

5

6

7

8

9

10

PLL1707/8

FS2 (MC)

VCC

AGND

XT1

DGND2

MCKO2

MCKO1

VDD2

CSEL

XT2

VDD1

1

2

3

4

SCKO2

SCKO3

DGND1

20

19

18

17

VDD3

SCKO1

SCKO0

DGND3

3.3 V

(1)

(1)

(2)

(4)

(3)

(3)

(1)

(2)

Clock Outputs (5)

(1)

(1) 0.1-

µF ceramic capacitor typical, depending on quality of power supply and pattern layout

(2) 10-

µF aluminum electrolytic capacitor typical, depending on quality of power supply and pattern layout

(3) 27-MHz quartz crystal and 10–33 pF

× 2 ceramic capacitors, which generate the appropriate amplitude of oscillation on XT1/XT2

(4) This connection is for PLL1707 (parallel mode); when PLL1708 (serial mode) is to be used, control pins must be connected to serial interfaced

controller.

(5) For good jitter performance, minimize the load capacitance on the clock output. It is recommended to drive the clock outputs through buffers,

especially if there are heavy loads on SCKO0 and SCKO1, and to minimize mutual interference by separating them or inserting a guard pattern

between them.

Figure 15. Typical Connection Diagram