PLL1707

PLL1708

SLES065 – DECEMBER 2002

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14

Program-Register Bit Mapping

The built-in functions of the PLL1708 are controlled through a 16-bit program register. This register is loaded using MD,

MC and MS. After the 16 data bits are clocked in using the rising edge of MC, MS is used to latch the data into the register.

Table 6 shows the bit mapping of the register. The serial mode control format and control data input timing are shown in

Figure 13 and Figure 14, respectively.

MS

MC

MD

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Figure 13. Serial Mode Control Format

t(MSL)

VDD/2

MC

MD

MSB

MS

t(MHH)

VDD/2

VDD/2

t(MSS)

t(MSH)

t(MCL)

t(MCH)

LSB

t(MDH)

t(MCY)

t(MDS)

t(MSS)

DESCRIPTION

SYMBOL

MIN

TYP

MAX

UNIT

MC pulse cycle time

t(MCY)

100

ns

MC pulse duration LOW

t(MCL)

40

ns

MC pulse duration HIGH

t(MCH)

40

ns

MD hold time

t(MDH)

40

ns

MD setup time

t(MDS)

40

ns

MS low-level time

t(MSL)

16

MC clocks(1)

MS high-level time

t(MHH)

200

ns

MS hold time(2)

t(MSH)

40

ns

MS setup time(3)

t(MSS)

40

ns

(1) MC clocks: MC clock period

(2) MC rising edge for LSB to MS rising edge

(3) MS rising edge to the next MC rising edge. If the MC clock is stopped after the LSB, any MS rise time is accepted.

Figure 14. Control Data Input Timing