X84160IG datasheet(5/22 Pages) ICMIC

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X84160/640/128

CONTROL REGISTER

The X84160/640/128 has one register that contains

control bits for the devices. The control bits, WPEN, BP1,

and BP0, are shown in Table 1. To read or change the

contents of this register requires a one byte operation to

address FFFFh.

A read from FFFFh returns the one byte contents of the

control register unused bits return 0. Continued reads

return undeﬁned data. A write to address FFFFh changes

the value of the bits. Unused bits are written as “0”.

Writing more than one byte to the control register is a

violation and the operation will be aborted. After sending

one byte to the control register, a start nonvolatile write

cycle will latch in the new state.

Table 1

WPEN: Write Protect Enable Bit

The Write-Protect-Enable (WPEN) bit is an enable bit for

the WP pin.

Table 2

654

WPEN

BP1

BP0

WPEN

Protected

Blocks

Unprotected

Blocks

Status

Protected

Writable

LOW

Protected

Writable

Protected

HIGH

Protected

Writable

The Write Protect (WP) pin and the nonvolatile Write

Protect Enable (WPEN) bit in the Status Register control

the programmable hardware write protect feature.

Hardware write protection is enabled when WP pin is

LOW, and the WPEN bit is “1”. Hardware write protection

is disabled when either the WP pin is HIGH or the WPEN

bit is “0”. When the chip is hardware write protected,

nonvolatile write is disabled to the Control Register,

including the Block Protect bits and the WPEN bit itself,

as well as the block-protected sections in the memory

array. Only the sections of the memory array that are not

block-protected can be written.

Note:

When the WP pin is tied to VSS and the WPEN bit is HIGH, the

WPEN bit is write protected. It cannot be changed back to a

“0”, as long as the WP pin is held LOW.

BP1, BP0: Block Protect Bits

The Block Protect (BP0 and BP1) bits are nonvolatile and

allow the user to select one of four levels of protection.

The X84160/640/128 is divided into four segments. One,

two, or all four of the segments may be protected. That is,

the user may read the segments but will be unable to

alter (write) data within the selected segments. The

partitioning is controlled as illustrated in table 3 below.

Table 3. Block Lock Protection

Control Register Bits

Array Address Protected

BP1

BP0

X84160

X84640

X84128

Array

None

0600h–07FFh

1800h–1FFFh

3000h–3FFFh

upper 1/4

0400h–07FFh

1000h–1FFFh

2000h–3FFFh

upper 1/2

0000–07FFh

0000–1FFFh

0000h–3FFFh

Full Array

(Not including the

control register.)

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