TLV5627C, TLV5627I

2.7V TO 5.5V 8BIT 4CHANNEL DIGITALTOANALOG CONVERTERS

WITH POWER DOWN

SLAS232A − JUNE1999 − REVISED JULY 2002

14

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

In power-down mode, all amplifiers within the TLV5627 are disabled. A particular DAC (A, B, C, D) of the

TLV5627 is selected by A1 and A0 within the input word.

A1

A0

DAC

0

0

A

0

1

B

1

0

C

1

1

D

TLV5627 interfaced to TMS320C203 DSP

hardware interfacing

Figure 17 shows an example of how to connect the TLV5627 to a TMS320C203 DSP. The serial port is

configured in burst mode, with FSX generated by the TMS320C203 to provide the frame sync (FS) input to the

TLV5627. Data is transmitted on the DX line, with the serial clock input on the CLKX line. The general-purpose

input/output port bits IO0 and IO1 are used to generate the chip select ( CS ) and DAC latch update ( LDAC )

inputs to the TLV5627. The active low power down ( PD ) is pulled high all the time to ensure the DACs are

enabled.

DX

CLKX

FSX

I/O 0

I/O 1

TMS320C203

SDIN

SCLK

FS

CS

LDAC

REF

VDD

PD

VOUTA

VOUTB

VOUTC

VOUTD

VSS

TLV5627

REFINAB

REFINCD

Figure 17. TLV5627 Interfaced with TMS320C203