TLV5627C, TLV5627I

2.7V TO 5.5V 8BIT 4CHANNEL DIGITALTOANALOG CONVERTERS

WITH POWER DOWN

SLAS232A − JUNE1999 − REVISED JULY 2002

6

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range

(unless otherwise noted) (continued)

analog output dynamic performance

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SR

Output slew rate

CL = 100 pF, RL = 10 kΩ,

VO = 10% to 90%,

Fast

5

V/

µs

SR

Output slew rate

LL

VO = 10% to 90%,

Vref = 2.048 V, 1024 V

Slow

1

V/

µs

ts

Output settling time

To

± 0.1 LSB, CL = 100 pF,

Fast

2.5

4

s

ts

Output settling time

To

± 0.1 LSB, CL = 100 pF,

RL = 10 kΩ, See Notes 12 and 14

Slow

8.5

18

µs

ts(c)

Output settling time, code to code

To

± 0.1 LSB, CL = 100 pF,

Fast

1

s

ts(c)

Output settling time, code to code

To

± 0.1 LSB, CL = 100 pF,

RL = 10 kΩ, See Notes 13 and 14

Slow

2

µs

Glitch energy

Code transition from 7F0 to 800

10

nV-sec

SNR

Signal-to-noise ratio

Sinewave generated by DAC,

57

S/(N+D)

Signal to noise + distortion

Sinewave generated by DAC,

Reference voltage = 1.024 at 3 V and 2.048 at 5 V,

49

dB

THD

Total harmonic distortion

Reference voltage = 1.024 at 3 V and 2.048 at 5 V,

fs = 400 KSPS, fOUT = 1.1 kHz sinewave,

CL = 100 pF,

RL = 10 kΩ,

BW = 20 kHz

−50

dB

SFDR

Spurious free dynamic range

fs = 400 KSPS, fOUT = 1.1 kHz sinewave,

CL = 100 pF,

RL = 10 kΩ,

BW = 20 kHz

60

NOTES: 12. Settling time is the time for the output signal to remain within

± 0.1 LSB of the final measured value for a digital input code change

of 0x020 to 0xFF0 or 0xFF0 to 0x020.

13. Settling time is the time for the output signal to remain within

± 0.1 LSB of the final measured value for a digital input code change

of one count.

14. Limits are ensured by design and characterization, but are not production tested.

digital input timing requirements

MIN

NOM

MAX

UNIT

tsu(CS−FS)

Setup time, CS low before FS

↓

10

ns

tsu(FS−CK)

Setup time, FS low before first negative SCLK edge

8

ns

tsu(C16−FS)

Setup time, sixteenth negative SCLK edge after FS low on which bit D0 is sampled before

rising edge of FS

10

ns

tsu(C16−CS)

Setup time. The first positive SCLK edge after D0 is sampled before CS rising edge. If FS

is used instead of the SCLK positive edge to update the DAC, then the setup time is between

the FS rising edge and CS rising edge.

10

ns

twH

Pulse duration, SCLK high

25

ns

twL

Pulse duration, SCLK low

25

ns

tsu(D)

Setup time, data ready before SCLK falling edge

8

ns

th(D)

Hold time, data held valid after SCLK falling edge

5

ns

twH(FS)

Pulse duration, FS high

20

ns