TLV5627C, TLV5627I

2.7V TO 5.5V 8BIT 4CHANNEL DIGITALTOANALOG CONVERTERS

WITH POWER DOWN

SLAS232A − JUNE1999 − REVISED JULY 2002

15

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

TLV5627 interfaced to MCS51 microcontroller

hardware interfacing

Figure 18 shows an example of how to connect the TLV5627 to an MCS51 Microcontroller. The serial DAC

input data and external control signals are sent via I/O Port 3 of the controller. The serial data is sent on the RxD

line, with the serial clock output on the TxD line. Port 3 bits 3, 4, and 5 are configured as outputs to provide the

DAC latch update (LDAC), chip select (CS) and frame sync (FS) signals for the TLV5627. The active low power

down pin (PD) of the TLV5627 is pulled high to ensure that the DACs are enabled.

RxD

TxD

P3.3

P3.4

MCS

®51

SDIN

SCLK

FS

CS

LDAC

REF

VDD

PD

VOUTA

VOUTB

VOUTC

VOUTD

VSS

TLV5627

P3.4

REFINAB

REFINCD

Figure 18. TLV5627 Interfaced with MCS51

linearity, offset, and gain error using single ended supplies

When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With

a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage

may not change with the first code, depending on the magnitude of the offset voltage.

The output amplifier attempts to drive the output to a negative voltage. However, because the most negative

supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.

The output voltage then remains at zero until the input code value produces a sufficient positive output voltage

to overcome the negative offset voltage, resulting in the transfer function shown in Figure 19.

DAC Code

Output

Voltage

0 V

Negative

Offset

Figure 19. Effect of Negative Offset (single supply)

MCS is a registered trademark of Intel Corporation.