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TPL5000 Datasheet(PDF) 6 Page - Texas Instruments |
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TPL5000 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 22 page ![]() t5 tDTCAL WAKE PGOOD DONE RSTn tDTCAL trTCAL tfTCAL tCAL ttDPt ttDPt ttDPt ttDDONEt tDONE trRSTn tfRSTn tRSTn ttDDONEt trWAKE tfWAKE TCAL TPL5000 SNAS628B – JULY 2013 – REVISED DECEMBER 2014 www.ti.com 7.6 Timing Requirements MIN TYP MAX UNIT trTCAL Rise Time TCAL Capacitive load 15 pF 50 ns tfTCAL, Fall Time TCAL Capacitive load 15 pF 50 ns trRSTn, Rise Time RSTn Capacitive load 15 pF, Rpull-up 100Kohm 4 ns tfRSTn, Fall Time RSTn Capacitive load 15 pF, Rpull-up 100Kohm 50 ns trWAKE Rise Time WAKE Capacitive load 15 pF 50 ns tfWAKE Fall Time WAKE Capacitive load 15 pF 50 ns Min delay 100 ns DONE to RSTn or WAKE tDDONE delay Max delay tDP-5*tCAL ms tDTCAL TCAL to RSTn or WAKE tCAL/2 ms delay Figure 1. Timing Diagram 6 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPL5000 |
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