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TPL5000 Datasheet(PDF) 8 Page - Texas Instruments |
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TPL5000 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 22 page ![]() LOW POWER OSCILLATOR CONTROL FREQUENCY DIVIDER D0 D1 D2 RSTn WAKE TCAL DONE PGOOD GND VDD TPL5000 SNAS628B – JULY 2013 – REVISED DECEMBER 2014 www.ti.com 8 Detailed Description 8.1 Overview The TPL5000 is a long-term timer with a watchdog feature for low-power applications. The TPL5000 is designed for use in interrupt-driven applications and provides selectable timing from 1 s to 64 s. An additional supervisor feature is achieved through interfacing the TPL5000 to a power-management IC. 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Supervisor Feature A critical event that can corrupt the memory of a microcontroller is a voltage supply drop (supply lower than minimum operating range), and a reset of the microcontroller is mandatory if this occurs. Since the TPL5000 is the right choice in systems which stay most of the time in deep sleep, due to its ultra-low power consumption, it is fundamental that it takes into account the voltage drop events. The TPL5000 implements a supervisory functionality when working with some power-management ICs which indicate the status of the supply voltage with a power-good or battery-good output. The supervisory functionality is enabled by simply connecting the Battery management power-good output to the TPL5000 PGOOD pin. If this feature is not used connect the PGOOD pin to VDD. In case the power management IC detects a voltage drop, lowering the PGOOD line, while the microcontroller is in deep sleep mode (in which internal supervisors are usually off), the TPL5000 internally latches that event, and when the PGOOD returns to high, it sends out a RESET signal to the microcontroller at the end of the elapsed delay period. Figure 6 shows the supervisor feature of the TPL5000. The sequence F, G is a standard sequence where the microcontroller is in deep sleep and a voltage supply drop occurs (which is highlighted by the PGOOD high to low transition). When PGOOD is high again, a reset pulse at the end of the delay period is sent to the microcontroller (arrow F), then the microcontroller executes its routine (memory has been reloaded upon reset) and sends the "DONE" signal. 8 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPL5000 |
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