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ADS6145 Datasheet(PDF) 49 Page - Texas Instruments |
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ADS6145 Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 68 page ![]() www.ti.com POWER-DOWN MODES Global Power Down Standby Output Buffer Disable Input Clock Stop Power Supply Sequence ADS6145, ADS6144 ADS6143, ADS6142 SLWS198A – JULY 2007 – REVISED OCTOBER 2007 The ADS614X have four power-down modes – global power down, standby, output buffer disable, and input clock stopped. These modes can be set using the serial interface or using the parallel interface (pins SDATA and PDN). Table 14. Power-Down Modes POWER-DOWN PARALLEL INTERFACE SERIAL INTERFACE TOTAL POWER, WAKE-UP TIME MODES REGISTER BIT mW (to valid data) SDATA PDN (Table 5) Normal operation Low Low <PDN OBUF>=0 and 417 - <STBY>=0 Standby Low High <PDN OBUF>=0 and 72 Slow (15 µs) <STBY>=1 Output buffer disable High Low <PDN OBUF>=1 and 408 Fast (200 ns) <STBY>=0 Global power down High High <PDN OBUF>=1 and 30 Slow (15 µs) <STBY>=1 In this mode, the A/D converter, internal references, and the output buffers are powered down and the total power dissipation reduces to about 30 mW. The output buffers are in a high-impedance state. The wake-up time from the global power down to output data becoming valid in normal mode is a maximum of 50 µs. Note that after coming out of global power down, optimum performance is achieved after the internal reference voltages have stabilized (about 1 ms). Only the A/D converter is powered down and total power dissipation is approximately 72 mW. The wake-up time from standby to output data becoming valid is a maximum of 50 µs. The data output buffers can be disabled, reducing total power to about 408 mW. With the buffers disabled, the outputs are in a high-impedance state. The wake-up time from this mode to data becoming valid in normal mode is a maximum of 500 ns in LVDS mode and 200 ns in CMOS mode. The converter enters this mode when the input clock frequency falls below 1 MSPS. Power dissipation is approximately 120 mW, and the wake-up time from this mode to data becoming valid in normal mode is a maximum of 50 µs. During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are separated inside the device. Externally, they can be driven from separate supplies or from a single supply. Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 49 Product Folder Link(s): ADS6145, ADS6144 ADS6143, ADS6142 |
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