ADS6145 datasheet(16/68 Pages) TI

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DESCRIPTION OF SERIAL REGISTERS

ADS6145, ADS6144

ADS6143, ADS6142

SLWS198A – JULY 2007 – REVISED OCTOBER 2007

Each register function is explained in detail.

Table 5.

A4–A0

D10

(hex)

<COARSE

<REF>

<RST>

<STBY>

Output buffers

GAIN>

LVDS or CMOS

Internal or

Software

Output clock

ADC Power

powered down

Coarse gain

Output interface

external

reset

buffer powered

down

reference

down

<STBY> Power down modes

Normal operation

Device enters standby mode where only ADC is powered down.

<PDN CLKOUT> Power down modes

Output clock is active (on CLKOUT pin)

Output clock buffer is powered down and becomes three-stated. Data outputs are unaffected.

<RST>

Software reset applied - resets all internal registers and the bit self-clears to 0.

<REF> Reference selection

Internal reference enabled

External reference enabled

<LVDS CMOS> Output Interface selection

Parallel CMOS interface

DDR LVDS Interface

<COARSE GAIN> Gain programming

0 dB Coarse gain

3.5 dB Coarse gain

D10

<PDN OBUF> Power down modes

Output data and clock buffers enabled

Output data and clock buffers disabled

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ADS6145 Datasheet(PDF) 16 Page - Texas Instruments

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