OPA548 datasheet(19/36 Pages) TI

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OPEN-LOOP GAIN LINEARITY

SETTLING TIME

-50

-40

-30

-20

-10

OutputVoltage(V)

isaFunctionofV

andI

OUT

LOAD

T =+25 C

L =1880W,1mV/div

89dB

106dB

74dB

L =900W,2mV/div

R =4.87kW

,200 V/div

10kW

InvertingResponse

MeasuredHere,V

CombinationofBoth

Invertingand

NoninvertingResponses,V

-IN

+IN

OUT

OPA454

OUT

-IN

+IN

OPA454

SBOS391 – DECEMBER 2007

Figure 65 shows the nonlinear relationship of AOL and

The circuit in Figure 66 is used to measure the

output voltage. As Figure 65 shows, open-loop gain is

settling time response. The left half of the circuit is a

lower with positive output voltage levels compared to

standard, false-summing junction test circuit used for

negative

voltage

levels.

Specifications

the

settling time and open-loop gain measurement. R1

Electrical Characteristics table are based upon the

and R2 provide the gain and allow for measurement

average gain measured at both output extremes.

without connecting a scope probe directly to the

summing junction, which can disturb proper op amp

function by causing oscillation.

The right half of the circuit looks at the combination of

both inverting and noninverting responses. R5 and R6

remove the large step response. The remaining

voltage at V2 shows the small-signal settling time that

is centered on zero. This test circuit can be used for

incoming inspection, real-time measurement, or in

designing

compensation

circuits

system

applications.

Table 2. Settling Time Measurement Circuit

Configuration Using Different Gain Settings for

Figure 66

GAIN

COMPONENT

Figure 65. Differential Input Voltage (+IN to –IN)

R1 (Ω)

10k

versus Output Voltage

R3 (Ω)

10k

R7 (Ω)

10k

R8 (Ω)

∞

VIN (VPP)

Figure 66. Settling Time Test Measurement Circuit

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