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SIC1182K Datasheet(PDF) 5 Page - Power Integrations, Inc.

Part # SIC1182K
Description  SCALE-iDriver Family
PDF  16 Pages
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Manufacturer  POWERINT [Power Integrations, Inc.]
Direct Link  http://www.powerint.com
Logo POWERINT - Power Integrations, Inc.

SIC1182K Datasheet(HTML) 5 Page - Power Integrations, Inc.

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Rev. D 09/19
5
SIC1182K
www.power.com
Figure 7.
Primary-Side of Example Circuitry.
Application Example
This example describes how to set up the SIC1182K to use overvoltage
limitation with a chain of TVS-diodes between the SiC MOSFET device
Drain and SIC1182K SNS pin as well as a short-circuit detection via a
resistive network also connected to the SNS pin.
Primary-Side
For the input the circuitry of Figure 6 is recommended, when using
15 V input logic. R
1 and R2 represent a voltage divider to get a 5 V
signal at the IN pin. If additional filtering is required a capacitor C
F can
be placed in parallel to R
2 as depicted in Figure 7. The time constant
τ can be calculated by Equation (1). In case direct 5 V logic is used at
the IN pin, R
2 can be omitted and R1 can be reduced to 100 Ω.
(1)
t
RR
RR
CF
12
12
#
#
=
+
The pull up resistor R
SO shall be connected to VCC and SO, with a
value of 1 kΩ, to provide at least 5 mA to SO (open drain) in a fault
condition. The primary-side power supply is connected to VCC and
COM, where C1 is buffering V
VCC and C2 acts as high frequency filter.
Secondary-Side
The secondary-side power supply is connected to VISO and COM as
shown in Figure 8. It is for instance recommended for SiC MOSFET
to use V
TOT = 20 V, to get VGH = 15 V for turn-on referenced to VEE
and V
GL = -5 V referenced to VEE for turn-off, to avoid additional
components.
For each µC of semiconductor’s gate charge a buffer capacitor of at
least 3 µF shall be placed at VEE to COM (C
S1) as well as between
VISO and VEE (C
S2). A 10 nF capacitor is connected between GH and
VGXX.
To ensure gate voltage stabilization and drain current limitation
during short-circuit the gate is connected to V
VISO through Schottky
diode D
STO.
To avoid parasitic turn-on during system power-on, the gate is
connected to COM via a 22 kΩ resistor R
DIS.
The SNS pin has an alternating function that can be used for an
overvoltage limitation, the so called Advanced Active Clamping,
via a TVS-diodes chain during the turn-off transient as well as for
a short-circuit detection via a resistive network during the turn-on
transient.
The Advanced Active Clamping is triggered with the current I
SNS
flowing into the SNS pin of the SIC1182K which gradually reduces the
GL-current down to typically 20 mA with increased I
SNS. This increas-
es the effectiveness of the Basic Active Clamping function provided
by the TVS-diodes drastically. The total voltage limit of the TVS chain
is set to 900 V for a 1200 V-SiC MOSFET device.
During the turn-on transient the SNS pin serves the short-circuit
detection and shut-down is triggered by a detection level referenced
to VEE of V
SNS. The resistor chain to the Drain of the SiC MOSFET
consisting of the resistors from R
CE2 to RCE10 has a total resistance of
2.43 MΩ for a 1200 V-SiC MOSFET device.
If the SiC MOSFET has a sense terminal referenced to VEE which pro-
vide a fraction of the actual Source current this signal can also be fed
back to the SNS pin via a shunt resistor. If here the SNS detection
level of V
SNS is reached the SIC1182K will turn-off the SiC MOSFET and
thus provide an over-current detection.
Figure 8. Secondary-Side of Example Circuitry.
PI-8771-071718
SCALE-iDriver
IN
SO
VCC
GND
RSO
R2
R1
C1
CF
C2
PI-8896-011119
SCALE-iDriver
SNS
GH
VISO
VGXX
GL
VEE
COM
VTOT
+
-
CS2
CGXX
RGON
RCE1
S1
D
S2
G
RGOFF
DSTO
DACC3
DACC2
RDIS
RACC2
RCETH
DACC1
RACC1
CS1
CCOMPS
CAAC1
RCE2
RCE3
DTVS1
DTVS2
DTVS3
DTVS4
DTVS5
DTVS6
RCE4
RCE5
RCE6
RCE7
RCE8
RCE9
RCE10



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