TAS3103ADBT datasheet(62/152 Pages) TI

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2−28

Table 2−6. GPIO Port Functionality—I2C Master Mode

GPIO PORT

FUNCTION

GPIO0 (pin 18)

Volume up—CH1 and CH2

GPIO1 (pin 19)

Volume down—CH1 and CH2

GPIO2 (pin 20)

Volume up—CH3

GPIO3 (pin 21)

Volume down—CH3

GPIOFSCOUNT also governs the rate at which the power-down pin PWRDN is sampled and the rate at which the

watchdog counter is reset. GPIOFSCOUNT then cannot be independently used to tune the volume adjustment. For

this reason, bit field GPIO_samp_int of the same I2C subaddress (0xEF) is included to provide the ability to adjust

the responsiveness (or sluggishness) of the volume switches.

Each GPIO port has a weak pullup to VDDS. A volume control switch then typically switches the signal line to the GPIO

port between ground and an open circuit. The parameter GPIO_samp_int sets how many consecutive GPIO port

samples must be logic 0 before a logic 0 is read. A read logic 0 on a given GPIO port is interpreted as a command

to increase or decrease volume. If a logic 0 is read, and the signal level into the GPIO port remains at logic 0 for another

GPIO_samp_int consecutive samples, a second logic 0 value is read.

For each logic 0 read, the volume is increased or decreased 0.5 dB. After two consecutive logic 0 readings, each logic

0 reading that follows results in the volume level increasing or decreasing 5 dB instead of 0.5 dB. Figure 2−24 shows

an example of activating a volume switch. For the example in Figure 2−24, GPIOFSCOUNT is set to 3 and

GPIO_samp_int is set to 2. It is also noted in Figure 2−24 that the parameter GPIO_samp_int only comes into play

on logic 0 valued samples. As soon as the GPIO sample goes to logic 1, the audio updating ceases.

2.8.2

GPIO Functionality—I2C Slave Mode

In the I2C slave mode, the GPIO ports can be used as true general-purpose ports. Each port can be individually

programmed, via the I2C bus, to be either an input or an output port. The default assignment for all GPIO ports, in

the I2C slave mode, is an input port.

When a given GPIO port is programmed as an output port, by setting the appropriate bit in the bit field GPIODIR

(19:16) of subaddress 0xEF to logic 1, the logic level output is set by the logic level programmed into the appropriate

bit in bit field GPIO_in_out (3:0) of subaddress 0xEE. The I2C bus then controls the logic output level for those GPIO

ports assigned as output ports.

When a given GPIO port is programmed as an input port by setting the appropriate bit in bit field GPIODIR (19:16)

of subaddress 0xEF to logic 0, the logic input level into the GPIO port is written to the appropriate bit in bit field

GPIO_in_out (3:0) of subaddress 0xEE. The I2C bus can then be used to read bit field GPIO_in_out to determine

the logic levels at the input GPIO ports. Whether a given bit in the bit field GPIO_in_out is a bit to be read via the I2C

bus or a bit to be written to via the I2C bus is strictly determined by the corresponding bit setting in bit field GPIODIR.

In the I2C slave mode, the GPIO input ports are read every GPIOFSCOUNT LRCLKs, as was the case in the I2C

master mode. However, parameter GPIO_samp_int does not have a role in the I2C slave mode. If a GPIO port is

assigned as an output port, a logic 0 bit value is supplied by the TAS3103A for this GPIO port in response to a read

transaction at subaddress 0xEE.

If the GPIO ports are left in their power turnon default state, they are input ports with a weak pullup on the input to

VDSS.

TAS3103ADBT Datasheet(PDF) 62 Page - Texas Instruments

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