VDD

IN

ENABLE

OUT

VSS

OSC

1V

C1

LMV112

www.ti.com

SNAS297B – MAY 2005 – REVISED MAY 2013

APPLICATION INFORMATION

GENERAL

The LMV112 is designed to minimize the effects of spurious signals from the base band chip to the oscillator.

Also the influence of varying load resistance and capacitance to the oscillator is minimized, while the drive

capability is increased.

The inputs of the LMV112 are internally biased at 1V, making AC coupling possible without external bias

resistors.

To optimize current consumption, the buffer not in use can be disabled by connecting the enable pin to VSS.

The LMV112 has no internal ground reference; therefore, either single or split supply configurations can be used.

The LMV112 is an easy replacement for discrete circuitry. It simplifies board layout and minimizes the effect of

layout related parasitic components.

INPUT CONFIGURATION

AC coupling is made possible by biasing the input. A large DC load at the oscillator input could change the load

impedance and therefore it’s oscillating frequency. To avoid external resistors the inputs are internally biased.

This biasing is set at 1V as depicted in Figure 36. Because this biasing is set at 1V, the maximum amplitude of

the AC signal is 2 VPP.

The coupling capacitance should be large enough to let the AC signal pass. This is a unity gain buffer with rail-

to-rail inputs and outputs.

Figure 36. Input Configuration

FREQUENCY PULLING

Frequency pulling is the frequency variation of an oscillator caused by a varying load. In the typical application,

the load of the oscillator is a fixed capacitor (C1) and the input impedance of the buffer.

To keep the input impedance as constant as possible, the input is biased at 1V, even when the part is disabled.

A simplified schematic of the input configuration is shown in Figure 36.

Copyright © 2005–2013, Texas Instruments Incorporated

Submit Documentation Feedback

13

Product Folder Links: LMV112