PLL1707-Q1

www.ti.com

SLES259A

– JUNE 2010 – REVISED MARCH 2011

ELECTRICAL CHARACTERISTICS (continued)

TA = 25°C, VDD1-VDD3 (= VDD) = VCC = 3.3 V, fM = 27 MHz, crystal oscillation, fS = 48 kHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MASTER CLOCK (MCKO1, MCKO2) (fM = 27 MHz, C1 = C2 = 15 pF, CL = 20 pF on measurement pin)

Master clock frequency

26.73

27

27.27

MHz

VIH

0.7 VCC

Input level(4)(5)

V

VIL

0.3 VCC

IIH

VIN = VCC

±10

Input current(4)

µA

IIL

VIN = 0 V

±10

Output voltage(6)

3.5

Vp-p

Output rise time

20% to 80% of VDD

2

ns

Output fall time

80% to 20% of VDD

2

ns

For crystal oscillation

45

51

55 %

Duty cycle

For external clock

50

Clock jitter(7)

50

ps

Power-up time(8)

0.5

1.5

ms

PLL AC CHARACTERISTICS (SCKO0-SCKO3) (fM = 27 MHz, CL = 20 pF on measurement pin)

SCKO0

Fixed

33.8688

SCKO1

Selectable for 48 kHz

24.576

36.864

Output system clock frequency(9)

MHz

SCKO2

256 fS

8.192

12.288

24.576

SCKO3

384 fS

12.288

18.432

36.864

Output rise time

20% to 80% of VDD

2

ns

Output fall time

80% to 20% of VDD

2

ns

Output duty cycle

45

50

55

%

SCKO0, SCKO1

58

100

ps

Output clock jitter(7)(5)

SCKO2, SCKO3

50

100

ps

Frequency settling time(10)

To stated output frequency

50

150

ns

Power-up time(11)

To stated output frequency

3

6

ms

POWER SUPPLY

VCC, VDD

Supply voltage

2.7

3.3

3.6

V

IDD + ICC

Supply current(12)

VDD = VCC = 3.3 V, fS = 48 kHz

19

35

mA

Power dissipation

VDD = VCC = 3.3 V, fS = 48 kHz

63

130

mW

TEMPERATURE

Operating temperature

-40

85

°C

θJA

Thermal resistance

150

°C/W

(4)

Pin 10: XT1

(5)

Not production tested

(6)

Pin 11: XT2

(7)

Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter

performance varies with master clock mode, SCKO frequency setting and load capacitance on each clock output.

(8)

The delay time from power on to oscillation

(9)

The MIN and MAX values are the low and high selectable frequencies based on frequency (fS) selected (see Table 2 through Table 4)

(10) The settling time when the sampling frequency is changed

(11) The delay time from power on to lockup

(12) fM = 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with

sampling frequency selection and load condition.

Copyright

© 2010–2011, Texas Instruments Incorporated

Submit Documentation Feedback

3

Product Folder Link(s): PLL1707-Q1