SR

FS1

16

15

14

13

12

11

5

6

7

8

9

10

PLL1707

FS2

VCC

AGND

XT1

DGND2

MCKO2

MCKO1

VDD2

CSEL

XT2

VDD1

1

2

3

4

SCKO2

SCKO3

DGND1

20

19

18

17

VDD3

SCKO1

SCKO0

DGND3

3.3 V

(A)

(A)

(B)

(D)

(C)

(C)

(A)

(B)

Clock Outputs (E)

(A)

PLL1707-Q1

www.ti.com

SLES259A

– JUNE 2010 – REVISED MARCH 2011

Connection Diagram

Figure 12 shows the typical connection circuit for the PLL1707. There are four grounds for digital and analog

power supplies. However, the use of one common ground connection is recommended to avoid latch-up or other

power-supply-related troubles. Power supplies should be bypassed as close as possible to the device.

A.

0.1-

µF ceramic capacitor typical, depending on quality of power supply and pattern layout

B.

10-

µF aluminum electrolytic capacitor typical, depending on quality of power supply and pattern layout

C.

27-MHz quartz crystal and 10 pF to 33 pF

× 2 ceramic capacitors, which generate the appropriate amplitude of

oscillation on XT1/XT2

D.

This connection is for PLL1707 (parallel mode)

E.

For good jitter performance, minimize the load capacitance on the clock output. It is recommended to drive the clock

outputs through buffers, especially if there are heavy loads on SCKO0 and SCKO1, and to minimize mutual

interference by separating them or inserting a guard pattern between them.

Figure 12. Typical Connection Diagram

Copyright

© 2010–2011, Texas Instruments Incorporated

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Product Folder Link(s): PLL1707-Q1