PLL2

Counter N

Phase Detector

and

Loop Filter

OSC

Divider

SCKO3

384 fS

SCKO0−3

Frequency

Control

Counter M

VCO

Divider

PLL1

Counter M

Phase Detector

and

Loop Filter

Counter N

VCO

SCKO2

256 fS

Divider

SCKO1

36.864/24.576 MHz

SCKO0

33.8688 MHz

MCKO2

27 MHz

MCKO1

27 MHz

XT1 XT2

PLL1707-Q1

www.ti.com

SLES259A

– JUNE 2010 – REVISED MARCH 2011

THEORY OF OPERATION

Master Clock and System Clock Output

The PLL1707 consists of a dual PLL clock and master clock generator which generates four system clocks and

two buffered 27-MHz clocks from a 27-MHz master clock. Figure 7 shows the block diagram of the PLL1707. The

PLL is designed to accept a 27-MHz master clock.

Figure 7. Block Diagram

The master clock can be either a crystal oscillator placed between XT1 (pin 10) and XT2 (pin 11), or an external

input to XT1. If an external master clock is used, XT2 must be open. Figure 8 illustrates possible system clock

connection options, and Figure 9 illustrates the 27-MHz master clock timing requirement.

Copyright

© 2010–2011, Texas Instruments Incorporated

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Product Folder Link(s): PLL1707-Q1