PWM START REGISTER (0x18)

TAS5086

SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com

Bits D7 and D6: Define which start sequence is used, either low-Z or mid-Z. Not all power stages are compatible

with mid-Z; double-check the power-stage data sheet.

Bits D5–D0: Define which PWMs are used for charging the split capacitors and which PWMs should stay low,

indicating the output stages are to be held in Hi-Z under split-capacitor charging.

For most systems, this register is always 0x3F. The setting depends on how the power stage is connected.

Table 12. PWM Start Register (0x18)

D7

D6

D5

D4

D3

D2

D1

D0

FUNCTION

0

–

–

–

–

–

–

–

Use Low-Z sequence for part 1 of the start

1

–

–

–

–

–

–

–

Use Mid-Z sequence for part 1 of the start

–

0

–

–

–

–

–

–

Use Low-Z sequence for part 2 of the start

–

1

–

–

–

–

–

–

Use Mid-Z sequence for part 2 of the start

–

–

1

–

–

–

–

–

Start channel 6 under part 1 of the start

–

–

0

–

–

–

–

–

Start channel 6 under part 2 of the start

–

–

–

1

–

–

–

–

Start channel 5 under part 1 of the start

–

–

–

0

–

–

–

–

Start channel 5 under part 2 of the start

–

–

–

–

1

–

–

–

Start channel 4 under part 1 of the start

–

–

–

–

0

–

–

–

Start channel 4 under part 2 of the start

–

–

–

–

–

1

–

–

Start channel 3 under part 1 of the start

–

–

–

–

–

0

–

–

Start channel 3 under part 2 of the start

–

–

–

–

–

–

1

–

Start channel 2 under part 1 of the start

–

–

–

–

–

–

0

–

Start channel 2 under part 2 of the start

–

–

–

–

–

–

–

1

Start channel 1 under part 1 of the start

–

–

–

–

–

–

–

0

Start channel 1 under part 2 of the start

32

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