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PCA9570DP Datasheet(PDF) 16 Page - NXP Semiconductors |
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PCA9570DP Datasheet(HTML) 16 Page - NXP Semiconductors |
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16 / 32 page ![]() PCA9570 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4 — 17 September 2014 16 of 32 NXP Semiconductors PCA9570 Remote 4-bit general purpose outputs for 1 MHz I2C-bus 13. Dynamic characteristics [1] Fm+ mode on a non-standard, lightly loaded bus (<100 pF). [2] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. [3] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. [4] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns. Table 7. Dynamic characteristics VDD = 1.1 V to 3.6 V; VSS =0V; Tamb = 40 Cto+85 C; unless otherwise specified. Symbol Parameter Conditions Standard mode I2C-bus Fast mode I2C-bus 1MHz I2C-bus[1] Unit Min Max Min Max Min Max fSCL SCL clock frequency 0 100 0 400 0 1000 kHz tBUF bus free time between a STOP and START condition 4.7 - 1.3 - 0.5 - s tHD;STA hold time (repeated) START condition 4.0 - 0.6 - 0.26 - s tSU;STA set-up time for a repeated START condition 4.7 - 0.6 - 0.26 - s tSU;STO set-up time for STOP condition 4.0 - 0.6 - 0.26 - s tHD;DAT data hold time 0 - 0 - 0 - ns tVD;ACK data valid acknowledge time [2] - 3.45 - 0.9 - 0.45 s tVD;DAT data valid time [3] - 3.45 - 0.9 - 0.45 s tSU;DAT data set-up time 250 - 100 - 50 - ns tLOW LOW period of the SCL clock 4.7 - 1.3 - 0.5 - s tHIGH HIGH period of the SCL clock 4.0 - 0.6 - 0.26 - s tf fall time of both SDA and SCL signals -300 20 (VDD /5.5 V) 300 20 (VDD /5.5 V) 120 ns tr rise time of both SDA and SCL signals - 1000 20 300 - 120 ns tSP pulse width of spikes that must be suppressed by the input filter [4] -50 - 50 - 50 ns Port timing tv(Q) data output valid time - 200 - 200 - 200 ns |
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