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PCA9570DP Datasheet(PDF) 8 Page - NXP Semiconductors |
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PCA9570DP Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 32 page ![]() PCA9570 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4 — 17 September 2014 8 of 32 NXP Semiconductors PCA9570 Remote 4-bit general purpose outputs for 1 MHz I2C-bus 8. I/O programming 8.1 I/O architecture The device ports (see Figure 2) are entirely independent and are output ports. The state of the ports at the pin is transferred from the ports to the microcontroller in the Read mode (see Figure 13). Output data is transmitted to the ports in the Write mode (see Figure 12). At power-on all ports are HIGH. The state of the Output Port register determines if either Q1 or Q2 is on, driving the line either HIGH or LOW. A bit set to 1 in the data byte drives the line HIGH at the corresponding port. A bit set to 0 in the data byte drives the line LOW at the corresponding port. If an external voltage is applied to an output, care should be exercised because of the low-impedance path that exists between the pin and either VDD or VSS. 8.2 Writing to the port (Output mode) To write, the master (microcontroller) first addresses the slave device. By setting the last bit of the byte containing the slave address to logic 0, the Write mode is entered. The device acknowledges and the master sends the data byte for P7 to P0 and is acknowledged by the device. Writes to P7 to P4 are ignored in the PCA9570 as only P3 through P0 are available. The 4-bit data is presented on the port lines after it has been acknowledged by the device. The number of data bytes that can be sent successively is not limited. The previous data is overwritten every time a data byte has been sent. If more than 3 bytes are read, the slave device loops back to the first byte (manufacturer byte) and keeps sending data until the master generates a ‘no acknowledge’. Fig 11. Device ID field reading 002aah310 A6 A5 A4 A3 A2 A1 A0 I2C-bus slave address of the device to be identified A no acknowledge from master P STOP condition M 11 M 10 M9 M8 M7 M6 M5 M4 Sr repeated START condition 1 A R/W S 1 1 1 1 1 0 0 Device ID address START condition 0 A R/W acknowledge from one or several slaves x A don’t care acknowledge from slave to be identified 1 1 1 1 1 0 0 Device ID address acknowledge from slave to be identified A M3 M2 M1 M0 acknowledge from master manufacturer name = 000000000000 P8 P7 P6 P5 A acknowledge from master P4 P3 P2 P1 P0 R2 R1 R0 part identification = 100000000 revision = 000 |
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