DAC1282IPW datasheet(35/48 Pages) TI2

35 / 48 page

DAC1282, DAC1282A

www.ti.com

SBAS490B – DECEMBER 2011 – REVISED MAY 2015

Table 20. N: Sine Frequency N Register (address = 03h)

Bits[7:0]

N[7:0]: N register

These bits control the output frequency; see Equation 1.

Table 21. DCG0: DC Mode Digital Gain Byte 0, Least Significant Byte (address = 04h)

DCG7

DCG6

DCG5

DCG4

DCG3

DCG2

DCG1

DCG0

Table 22. DCG1: DC Mode Digital Gain Byte 1, Mid Byte (address = 05h)

DCG15

DCG14

DCG13

DCG12

DCG11

DCG10

DCG9

DCG8

Table 23. DCG2: DC Mode Digital Gain Byte 2, Most Significant Byte (address = 06h)

DCG23

DCG22

DCG21

DCG20

DCG19

DCG18

DCG17

DCG16

Bits[7:0]

DCG[23:0]: DC mode digital gain setting

The DCG0, DCG1, and DCG2 register bytes set the digital gain in dc mode; see Table 5.

Table 24. PULSA: Pulse Level A Byte (address = 07h)

PULSA4

PULSA3

PULSA2

PULSA1

PULSA0

Bits[7:5]

Reserved

Always write '0'.

Bits[4:0]

PULSA[4:0]: Pulse level A bits

These bits create pulse level A. (Selected output when SYNC is low.)

The PULSA and PULSB registers set two independent levels that can be used to provide pulse output. The

SYNC pin selects either level PULSA or level PULSB as the DAC output. The pulse amplitude resolution is

programmable in discrete steps, as shown in Table 6. Note that the pulse level value is independent of the

RANGE[2:0] setting.

Table 25. PULSB: Pulse Level B Byte (address = 08h)

PULSB4

PULSB3

PULSB2

PULSB1

PULSB0

Bits[7:5]

Reserved

Always write '0'.

Bits[4:0]

PULSB[4:0]: Pulse level B bits

These bits create pulse level B.

The PULSA and PULSB registers set two independent levels that can be used to provide pulse output. The

SYNC pin selects either level PULSA or level PULSB as the DAC output. The pulse amplitude resolution is

programmable in discrete steps; see Table 6. Note that the pulse level value is independent of the RANGE[2:0]

setting.

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