DLP9000 datasheet(8/58 Pages) TI2

8 / 58 page

DLP9000

DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016

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Pin Functions (continued)

PIN (1)

TYPE

(I/O/P)

SIGNAL

DATA

RATE (2)

INTERNAL

TERM (3)

DESCRIPTION

TRACE

(mils) (4)

NAME

NO.

CLOCKS

DCLK_AN

Input

LVDS

Differential

Clock, Negative

740

DCLK_BN

AJ5

Input

LVDS

Differential

Clock, Negative

740

DCLK_CN

C23

Input

LVDS

Differential

Clock, Negative

736

DCLK_DN

AH22

Input

LVDS

Differential

Clock, Negative

736

DCLK_AP

Input

LVDS

Differential

Clock, Positive

740

DCLK_BP

AJ3

Input

LVDS

Differential

Clock, Positive

740

DCLK_CP

C21

Input

LVDS

Differential

Clock, Positive

736

DCLK_DP

AH20

Input

LVDS

Differential

Clock, Positive

738

SERIAL COMMUNICATIONS PORT (SCP)

SCP_DO

AC3

Output

LVCMOS

SDR

Serial Communications Port Output

SCP_DI

AD2

Input

LVCMOS

SDR

Pull-Down

Serial Communications Port Data Input

SCP_CLK

AE1

Input

LVCMOS

Pull-Down

Serial Communications Port Clock

SCP_ENZ

AD4

Input

LVCMOS

Pull-Down

Active-low Serial Communications Port

Enable

MICROMIRROR RESET CONTROL

RESET_ADDR(0)

H12

Input

LVCMOS

Pull-Down

Reset Driver Address Select

RESET_ADDR(1)

Input

LVCMOS

Pull-Down

Reset Driver Address Select

RESET_ADDR(2)

Input

LVCMOS

Pull-Down

Reset Driver Address Select

RESET_ADDR(3)

A19

Input

LVCMOS

Pull-Down

Reset Driver Address Select

RESET_MODE(0)

Input

LVCMOS

Pull-Down

Reset Driver Mode Select

RESET_MODE(1)

Input

LVCMOS

Pull-Down

Reset Driver Mode Select

RESET_SEL(0)

AK4

Input

LVCMOS

Pull-Down

Reset Driver Level Select

RESET_SEL(1)

AL13

Input

LVCMOS

Pull-Down

Reset Driver Level Select

RESET_STROBE

Input

LVCMOS

Pull-Down

Reset Address, Mode, & Level latched on

rising-edge

ENABLES AND INTERRUPTS

PWRDNZ

Input

LVCMOS

Active-low Device Reset

RESET_OEZ

AK24

Input

LVCMOS

Pull-Down

Active-low output enable for DMD reset

driver circuits

RESETZ

AL19

Input

LVCMOS

Pull-Down

Active-low sets Reset circuits in known

VOFFSET state

RESET_IRQZ

Output

LVCMOS

Active-low, output interrupt to ASIC

VOLTAGE REGULATOR MONITORING

PG_BIAS

J19

Input

LVCMOS

Pull-Up

Active-low fault from external VBIAS

regulator

PG_OFFSET

A13

Input

LVCMOS

Pull-Up

Active-low fault from external VOFFSET

regulator

PG_RESET

AC19

Input

LVCMOS

Pull-Up

Active-low fault from external VRESET

regulator

EN_BIAS

J15

Output

LVCMOS

Active-high enable for external VBIAS

regulator

EN_OFFSET

H30

Output

LVCMOS

Active-high enable for external VOFFSET

regulator

EN_RESET

J17

Output

LVCMOS

Active-high enable for external VRESET

regulator

LEAVE PIN UNCONNECTED

MBRST(0)

Output

Analog

Pull-Down