DLP9000 datasheet(12/58 Pages) TI2

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DLP9000

DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016

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7.2 Storage Conditions

applicable before the DMD is installed in the final product

MIN

MAX

UNIT

TDMD

DMD storage temperature

-40

°C

Relative Humidity, (non-condensing)

95%

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 ESD Ratings

VALUE

UNIT

V(ESD)

Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)

±2000

(1)

Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.

(2)

All voltages are referenced to common ground VSS.

(3)

VOFFSET supply transients must fall within specified max voltages.

(4)

To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.

(5)

To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. Refer to Power Supply

Requirements for additional information.

(6)

Tester Conditions for VIH and VIL:

Frequency = 60 MHz. Maximum Rise Time = 2.5 ns at (20% to 80%)

Frequency = 60 MHz. Maximum Fall Time = 2.5 ns at (80% to 20%)

(7)

PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tri-states the

SCPDO output pin.

(8)

The SCP clock is a gated clock. Duty cycle shall be 50% ± 10%. SCP parameter is related to the frequency of DCLK.

(9)

Refer to Figure 1.

(10) SCP internal oscillator is specified to operate all SCP registers. For all SCP operations, DCLK is required.

7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

SUPPLY VOLTAGES (1) (2)

VCC

DLP9000

Supply voltage for LVCMOS core logic

3.0

3.3

3.6

DLP9000X

Supply voltage for LVCMOS core logic

3.3

3.45

3.6

VCCI

DLP9000

Supply voltage for LVDS receivers

3.0

3.3

3.6

DLP9000X

Supply voltage for LVDS receivers

3.3

3.45

3.6

VOFFSET

Supply voltage for HVCMOS and micromirror electrodes (3)

8.25

8.5

8.75

VBIAS

Supply voltage for micromirror electrodes

15.5

16.5

VRESET

–9.5

–10

–10.5

|VCCI–VCC| Supply voltage delta (absolute value) (4)

0.3

|VBIAS–VO

FFSET|

Supply voltage delta (absolute value) (5)

8.75

LVCMOS PINS

VIH

High level Input voltage (6)

1.7

2.5

VCC + 0.3

VIL

Low level Input voltage (6)

– 0.3

0.7

IOH

High level output current at VOH = 2.4 V

–20

IOL

Low level output current at VOL = 0.4 V

TPWRDNZ

PWRDNZ pulse width (7)

SCP INTERFACE

ƒclock

SCP clock frequency (8)

500

kHz

tSCP_SKEW

Time between valid SCPDI and rising edge of SCPCLK (9)

–800

800

tSCP_DELAY

Time between valid SCPDO and rising edge of SCPCLK (9)

700

tSCP_BYTE_INT

ERVAL

Time between consecutive bytes

µs

tSCP_NEG_ENZ Time between falling edge of SCPENZ and the first rising edge of SCPCLK

tSCP_PW_ENZ

SCPENZ inactive pulse width (high level)

µs

tSCP_OUT_EN

Time required for SCP output buffer to recover after SCPENZ (from tri-state)

1.5

ƒclock

SCP circuit clock oscillator frequency (10)

9.6

11.1

MHz

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