DLP9000 datasheet(11/58 Pages) TI2

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DLP9000

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DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016

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(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure above Recommended Operating Conditions for extended periods may affect device reliability.

(2)

All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for

proper DMD operation. VSS must also be connected.

(3)

VOFFSET supply transients must fall within specified voltages.

(4)

To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.

(5)

To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. Refer to Power Supply

Requirements for additional information.

(6)

This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.

(7)

LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.

(8)

Exposure of the DMD simultaneously to any combination of the maximum operating conditions for case temperature, differential

temperature, or illumination power density may affect device reliability.

(9)

The highest temperature of the active array as calculated by the Micromirror Array Temperature Calculation using ceramic test point 1

(TP1) in Figure 15.

(10) Temperature delta is the highest difference between the ceramic test point TP1 and window test points TP2 and TP3 in Figure 15.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

SUPPLY VOLTAGES

VCC

Supply voltage for LVCMOS core logic (2)

–0.5

VCCI

Supply voltage for LVDS receivers (2)

–0.5

VOFFSET

Supply voltage for HVCMOS and micromirror electrode (2) (3)

–0.5

VBIAS

Supply voltage for micromirror electrode (2)

–0.5

VRESET

Supply voltage for micromirror electrode (2)

–11

0.5

| VCC – VCCI |

Supply voltage delta (absolute value) (4)

0.3

| VBIAS – VOFFSET |

Supply voltage delta (absolute value) (5)

8.75

INPUT VOLTAGES

Input voltage for all other LVCMOS input pins (2)

–0.5

VCC + 0.3

Input voltage for all other LVDS input pins (2) (6)

–0.5

VCCI + 0.3

| VID |

Input differential voltage (absolute value) (7)

700

IID

Input differential current (7)

CLOCKS

ƒclock

DLP9000

Clock frequency for LVDS interface, DCLK_A

440

MHz

Clock frequency for LVDS interface, DCLK_B

440

Clock frequency for LVDS interface, DCLK_C

440

Clock frequency for LVDS interface, DCLK_D

440

DLP9000X

Clock frequency for LVDS interface, DCLK_A

500

Clock frequency for LVDS interface, DCLK_B

500

Clock frequency for LVDS interface, DCLK_C

500

Clock frequency for LVDS interface, DCLK_D

500

ENVIRONMENTAL

TARRAY

Array temperature: operational (8) (9)

ºC

Array temperature: non–operational (9)

-40

TWINDOW

Window temperature: operational

ºC

Window temperature: non–operational

-40

|TDELTA|

Absolute termperature delta between the window test points and the

ceramic test point TP1(10)

ºC

Relative Humidity, operating and non–operating

95%

DLP9000 Datasheet(PDF) 11 Page - Texas Instruments

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