6.3 Feature Description

6.3.1 SensorPath BUS SWD

SWD is the Single Wire Data line used for communication. SensorPath uses 3.3V single-ended signaling, with

a pull-up resistor and open-drain low-side drive (see Figure 6-1). For timing purposes SensorPath is designed

for capacitive loads (CL) of up to 400pF. Note that in many cases a 3.3V standby rail of the PC will be used

as a power supply for both the sensor and the master. Logic high and low voltage levels for SWD are TTL

compatible. The master may provide an internal pull-up resistor. In this case the external resistor is not needed.

The minimum value of the pull-up resistor must take into account the maximum allowable output load current of

4mA.

Master

RI

1.25k

Option

LM95010

V+

V+

RE

>1.25k

Option

CL

<400pF

SWD

SWD

Figure 6-1. SensorPath SWD simplified schematic

6.3.2 SensorPath BIT SIGNALING

Signals are transmitted over SensorPath using pulse-width encoding. There are five types of "bit signals":

• Data Bit 0

• Data Bit 1

• Start Bit

• Attention Request

• Reset

All the "bit signals" involve driving the bus to a low level. The duration of the low level differentiates between the

different "bit-signals". Each "bit signal" has a fixed pulse width. SensorPath supports a Bus Reset Operation and

Clock Training sequence that allows the slave device to synchronize its internal clock rate to the master. Since

the LM95010 meets the ±15% timing requirements of SensorPath, the LM95010 does not require the Clock

Training sequence and does support this feature. This section defines the "bit signal" behavior in all the modes.

Please refer to the timing diagrams in Electrical Characteristics (Figure 5-2 and Figure 5-3) while going through

this section. Note that the timing diagrams for the different types of "bit signals" are shown together to better

highlight the timing relationships between them. However, the different types of "bit signals" appear on SWD at

different points in time. These timing diagrams show the signals as driven by the master and the LM95010 slave

as well as the signal as seen when probing SWD. Signals labels that begin with the label Mout_ depict a drive by

the master. Signals labels that begin with the label Slv_ depict the drive by the LM95010. All other signals show

what would be seen when probing SWD for a particular function (e.g. "Master Wr 0" is the Master transmitting a

Data Bit with the value of 0).

6.3.3 Bus Inactive

The bus is inactive when the SWD signal is high for a period of at least tINACT. The bus is inactive between each

"bit signal".

6.3.4 Data Bit 0 and 1

All Data Bit signal transfers are started by the master. A Data Bit 0 is indicated by a "short" pulse; a Data Bit 1 is

indicated by a longer pulse. The direction of the bit is relative to the master, as follows:

• Data Write - a Data Bit transferred from the master to the LM95010.

• Data Read - a Data Bit transferred from the LM95010 to the master.

A master must monitor the bus as inactive before starting a Data Bit (read or Write).

www.ti.com

LM95010

SNIS133E – SEPTEMBER 2003 – REVISED FEBRUARY 2024

Copyright © 2024 Texas Instruments Incorporated

Submit Document Feedback

11

Product Folder Links: LM95010