A master initiates a data write by driving the bus active (low level) for the period that matches the data value

(tMtr0 or tMtr1 for a write of "0" or "1", respectively). The LM95010 will detect that the SWD becomes active within

a period of tSFEdet, and will start measuring the duration of that the SWD is active in order to detect the data

value.

A master initiates a data read by driving the bus for a period of tMtr0. The LM95010 will detect that the SWD have

become active within a period of tSFEdet. For a data read of "0", the LM95010 will not drive the SWD. For a data

read of "1" the LM95010 will start within tSFEdet to drive the SWD low for a period of tSLout1. Both master and

LM95010 must monitor the time at which the bus becomes inactive to identify a data read of "0" or "1".

During each Data Bit, both the master and all the LM95010s must monitor the bus (the master for Attention

Request and Reset; at the LM95010s for Start Bit, Attention Request and Reset) by measuring the time SWD

is active (low). If a Start Bit, Attention Requests or Reset "bit signal" is detected, the current "bit signal" is not

treated as a Data Bit.

Note that the bit rate of the protocol varies depending on the data transferred. Thus, the LM95010 has a value of

"0" in reserved or unused register bits for bus bandwidth efficiency.

6.3.5 Start Bit

A master must monitor the bus as inactive before beginning a Start Bit.

The master uses a Start Bit to indicate the beginning of a transfer. LM95010s will monitor for Start Bits all the

time, to allow synchronization of transactions with the master. If a Start Bit occurs in the middle of a transaction,

the LM95010 being addressed will abort the current transaction. In this case the transaction is not "completed"

by the LM95010 (see Section 6.3.8).

During each Start Bit, both the master and all the LM95010s must monitor the bus for Attention Request and

Reset, by measuring the time SWD is active (low). If an Attention Request or Reset condition is detected, the

current "bit signal" is not treated as a Start Bit. The master may attempt to send the Start Bit at a later time.

6.3.6 Attention Request

The LM95010 may initiate an Attention Request when the SensorPath bus is inactive.

Note that a Data Bit, or Start Bit, from the master may start simultaneously with an Attention Request from

the LM95010. In addition, two LM95010s may start an Attention Request simultaneously. Due to its length, the

Attention Request has priority over any other "bit signal", except Reset. Conflict with Data Bits and Start Bits are

detected by all the devices, to allow the bits to be ignored and re-issued by their originator.

The LM95010 will either check to see that the bus is inactive before starting an Attention Request, or start the

Attention Request with the tSFEdet time interval after SWD becomes active. The LM95010 will drive the signal low

for tSLoutA time. After this, both the master and the LM95010 must monitor the bus for a Reset Condition. If a

Reset condition is detected, the current "bit signal" is not treated as an Attention Request.

After Reset, an Attention Request can not be sent before the master has sent 14 Data Bits on the bus. See

Section 6.3.13 for further details on Attention Request generation.

6.3.7 Bus Reset

The LM95010 issues a Reset at power up. The master must also generate a Bus Reset at power-up for at

least the minimum reset time, it must not rely on the LM95010. SensorPath puts no limitation on the maximum

reset time of the master. Following a Bus Reset, the LM95010 may generate an Attention Request only after the

master has sent 14 Data Bits on the bus. See Section 6.3.13 for further details on Attention Request generation.

6.3.8 SensorPath BUS TRANSACTIONS

SensorPath is designed to work with a single master and up to seven slave devices. Each slave has a unique

address. The LM95010's supports up to 4 device addresses that are selected by the state of the address pins

ADD0 and ADD1. The Register Set of the LM95010 is defined in Section 7.

LM95010

SNIS133E – SEPTEMBER 2003 – REVISED FEBRUARY 2024

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