V

IN

V

REF

V

OUT

V

S = 5V

0.1µF

2.2µF

TLV3501

R

1 = 51Ω

R

2 = 10kΩ

V

HYST

( V

)

R

R

1

1

R

2

6mV

=

+

x

+

+

12

TLV3501, TLV3502

SBOS321E – MARCH 2005 – REVISED APRIL 2016

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Copyright © 2005–2016, Texas Instruments Incorporated

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Adding External Hysteresis

The TLV350x has a robust performance when used with a good layout. However, comparator inputs have little

noise immunity within the range of a specified offset voltage (±5 mV). For slow-moving or noisy input signals, the

comparator output can cause an undesirable switch state as input signals move through the switching threshold.

In such applications, the 6 mV of internal hysteresis of the TLV350x might not be sufficient. For greater noise

immunity, external hysteresis can be added by connecting a small amount of feedback to the positive input.

Figure 17 shows a typical topology used to introduce 25 mV of additional hysteresis, for a total of 31-mV

hysteresis when operating from a single 5-V supply. Use Equation 1 to calculate the approximate total hysteresis.

(1)

The total hysteresis, VHYST, sets the value of the transition voltage required to switch the comparator output, by

enlarging the threshold region, thereby reducing sensitivity to noise.

Figure 17. Adding Hysteresis to the TLV350x

8.2 Typical Application

8.2.1 Relaxation Oscillator

The TLV350x can easily be configured as a simple and inexpensive relaxation oscillator. In Figure 18, the R2

network sets the trip threshold at 1/3 and 2/3 of the supply. Because this circuit is a high-speed circuit, the

resistor values are low to minimize the effects of parasitic capacitance. The positive input alternates between 1/3

of V+ and 2/3 of V+, depending on whether the output is low or high. The time to charge (or discharge) is 0.69 ×

R1C. Therefore, the period is 1.38 × R1C. For 62 pF and 1 kΩ as shown in Figure 18, the output is calculated to

10.9 MHz. An implementation of this circuit oscillated at 9.6 MHz. Parasitic capacitance and component

tolerances explain the difference between theory and actual performance.