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MAX5083 Datasheet(PDF) 14 Page - Maxim Integrated Products

Part # MAX5083
Description  1.5A, 40V, MAXPower Step-Down DC-DC Converters
PDF  18 Pages
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX5083 Datasheet(HTML) 14 Page - Maxim Integrated Products

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1.5A, 40V, MAXPower Step-Down
DC-DC Converters
14
______________________________________________________________________________________
Since R3 >> R6, R3 + R6 can be approximated as R3.
R3 is then calculated as:
fP3 is set at 5xfC. Therefore, C8 is calculated as:
Power Dissipation
The MAX5082/MAX5083 is available in a thermally
enhanced package and can dissipate up to 2.7W at TA =
+70°C. When the die temperature reaches +160°C, the
part shuts down and is allowed to cool. After the part
cools by 20°C, the device restarts with a soft-start.
The power dissipated in the device is the sum of the
power dissipated from supply current (PQ), transition
losses due to switching the internal power MOSFET
(PSW), and the power dissipated due to the RMS cur-
rent through the internal power MOSFET (PMOSFET).
The total power dissipated in the package must be lim-
ited such that the junction temperature does not
exceed its absolute maximum rating of +150°C at maxi-
mum ambient temperature. Calculate the power lost in
the MAX5082/MAX5083 using the following equations:
The power loss through the switch:
PMOSFET = IRMS_MOSFET2 x RON
RON is the on-resistance of the internal power MOSFET
(see the Electrical Characteristics).
The power loss due to switching the internal MOSFET:
where tR and tF are the rise and fall times of the internal
power MOSFET measured at LX.
The power loss due to the switching supply current
(ISW):
PQ = VIN x ISW
The total power dissipated in the device will be:
PTOTAL = PMOSFET + PSW + PQ
Chip Information
TRANSISTOR COUNT: 4300
PROCESS: BiCMOS/DMOS
()
P
f
SW
SW
=
××
×
×
VI
t
t
IN
OUT
R
F
4
()
_
PI
R
II
I
I
I
D
II
I
II
I
MOSFET
RMS MOSFET
ON
RMS MOSFET
PK
PK
DC
DC
PK
OUT
PP
DC
OUT
PP
=×
=+
×
+
[]×
=+
=−
−
−
2
22
3
2
2
_
∆
∆
()
C
C
CR
f
8
7
27
5
1
=
××
×
−
π
P3
R
fC
3
1
26
≈
××
π LC
GAIN
(dB)
VOUT
REF
R3
COMP
R6
R5
C6
R4
FREQUENCY
CLOSED-LOOP
GAIN
EA
GAIN
fZ1 fZ2
fC
fP2
fP3
C8
EA
C7
Figure 4. Error Amplifier Compensation Circuit (Closed-Loop
and Error Amplifier Gain Plot) for Higher ESR Output Capacitors



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