68HC11

DAC082S085

PC7

SCK

MOSI

SCLK

DIN

SYNC

80C51/80L51

DAC082S085

P3.3

TXD

RXD

SCLK

DIN

SYNC

ADSP-2101/

ADSP2103

DAC082S085

TFS

DT

SCLK

DIN

SCLK

SYNC

17

DAC082S085

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SNAS365G – MAY 2006 – REVISED JUNE 2016

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Programming (continued)

8.4.3 DSP and Microprocessor Interfacing

Interfacing the DAC082S085 to microprocessors and DSPs is quite simple. The following guidelines are offered

to hasten the design process.

8.4.3.1 ADSP-2101/ADSP2103 Interfacing

Figure 31 shows a serial interface between the DAC082S085 and the ADSP-2101/ADSP2103. The DSP must be

set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT control

register and must be configured for Internal Clock Operation, Active Low Framing and 16-bit Word Length.

Transmission is started by writing a word to the TX register after the SPORT mode has been enabled.

Figure 31. ADSP-2101/2103 Interface

8.4.3.2 80C51/80L51 Interface

A serial interface between the DAC082S085 and the 80C51/80L51 microcontroller is shown in Figure 32. The

SYNC signal comes from a bit-programmable pin on the microcontroller. The example shown here uses port line

P3.3. This line is taken low when data is transmitted to the DAC082S085. Because the 80C51/80L51 transmits

8-bit bytes, only eight falling clock edges occur in the transmit cycle. To load data into the DAC, the P3.3 line

must be left low after the first eight bits are transmitted. A second write cycle is initiated to transmit the second

byte of data, after which port line P3.3 is brought high. The 80C51/80L51 transmit routine must recognize that

the 80C51/80L51 transmits data with the LSB first while the DAC082S085 requires data with the MSB first.

Figure 32. 80C51/80L51 Interface

8.4.3.3 68HC11 Interface

A serial interface between the DAC082S085 and the 68HC11 microcontroller is shown in Figure 33. The SYNC

line of the DAC082S085 is driven from a port line (PC7 in the figure), similar to the 80C51/80L51.

The 68HC11 must be configured with its CPOL bit as a zero and its CPHA bit as a one. This configuration

causes data on the MOSI output to be valid on the falling edge of SCLK. PC7 is taken low to transmit data to the

DAC. The 68HC11 transmits data in 8-bit bytes with eight falling clock edges. Data is transmitted with the MSB

first. PC7 must remain low after the first eight bits are transferred. A second write cycle is initiated to transmit the

second byte of data to the DAC, after which PC7 must be raised to end the write sequence.

Figure 33. 68HC11 Interface