DB15

DB0

SCLK

DIN

SYNC

tSYNC

tDS

tDH

tCL

tCH

1 / fSCLK

tCFSR

1

2

13

14

15

16

tSS

8

DAC082S085

SNAS365G – MAY 2006 – REVISED JUNE 2016

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Copyright © 2006–2016, Texas Instruments Incorporated

(1)

Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to AOQL (Average Outgoing

Quality Level).

(2)

This parameter is specified by design or characterization and is not tested in production.

7.6 Timing Requirements

The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code

range 3 to 252. All other limits are at TA = 25°C, unless otherwise specified.

(1)

MIN

TYP

MAX

UNIT

fSCLK

SCLK frequency

TA = 25°C

40

MHz

TMIN ≤ TA ≤ TMAX

30

ts

Output voltage settling time(2)

40h to C0h code change

RL = 2 kΩ, CL = 200 pF

TA = 25°C

3

µs

TMIN ≤ TA ≤ TMAX

4.5

SR

Output slew rate

1

V/µs

Glitch Impulse

Code change from 80h to 7Fh

12

nV-sec

Digital feedthrough

0.5

nV-sec

Digital crosstalk

1

nV-sec

DAC-to-DAC crosstalk

3

nV-sec

Multiplying bandwidth

VREFIN = 2.5 V ± 0.1 Vpp

160

kHz

Total harmonic distortion

VREFIN = 2.5 V ± 1 Vpp

input frequency = 10 kHz

70

dB

tWU

Wake-up time

VA = 3 V

6

µs

VA = 5 V

39

1/fSCLK

SCLK cycle time

TA = 25°C

25

ns

TMIN ≤ TA ≤ TMAX

33

tCH

SCLK high time

TA = 25°C

7

ns

TMIN ≤ TA ≤ TMAX

10

tCL

SCLK low time

TA = 25°C

7

ns

TMIN ≤ TA ≤ TMAX

10

tSS

SYNC setup time prior to

SCLK falling edge

TA = 25°C

4

ns

TMIN ≤ TA ≤ TMAX

10

tDS

Data setup time prior to SCLK

falling edge

TA = 25°C

1.5

ns

TMIN ≤ TA ≤ TMAX

3.5

tDH

Data hold time after SCLK

falling edge

TA = 25°C

1.5

ns

TMIN ≤ TA ≤ TMAX

3.5

tCFSR

SCLK fall prior to rise of

SYNC

TA = 25°C

0

ns

TMIN ≤ TA ≤ TMAX

3

tSYNC

SYNC high time

TA = 25°C

6

ns

TMIN ≤ TA ≤ TMAX

10

Figure 1. Serial Timing Diagram