6.5 Thermal Information

THERMAL METRIC(1)

DLP3010LC

UNIT

FQK (LGA)

57 PINS

Thermal resistance

Active area to test point 1 (TP1)(1)

5.4

°C/W

(1)

The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of

maintaining the package within the temperature range specified in the Section 6.4. The total heat load on the DMD is largely driven by

the incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and

electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window

clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)(10)

PARAMETER

TEST CONDITIONS(2)

MIN

TYP

MAX

UNIT

CURRENT

IDD

Supply current: VDD(3) (5)

VDD = 1.95 V

60.5

mA

VDD = 1.8 V

54

IDDI

Supply current: VDDI(3) (5)

VDDI = 1.95 V

16.5

mA

VDD = 1.8 V

11.3

IOFFSET

Supply current: VOFFSET(4) (6)

VOFFSET = 10.5 V

2.2

mA

VOFFSET = 10 V

1.5

IBIAS

Supply current: VBIAS(4) (6)

VBIAS = 18.5 V

0.6

mA

VBIAS = 18 V

0.3

IRESET

Supply current: VRESET(6)

VRESET = –14.5 V

2.4

mA

VRESET = –14 V

1.7

POWER(1)

PDD

Supply power dissipation: VDD(3) (5)

VDD = 1.95 V

118

mW

VDD = 1.8 V

97.2

PDDI

Supply power dissipation: VDDI(3) (5)

VDDI = 1.95 V

32

mW

VDD = 1.8 V

20

POFFSET

Supply power dissipation:

VOFFSET(4) (6)

VOFFSET = 10.5 V

23

mW

VOFFSET = 10 V

15

PBIAS

Supply power dissipation: VBIAS(4) (6)

VBIAS = 18.5 V

11

mW

VBIAS = 18 V

6

PRESET

Supply power dissipation: VRESET(6)

VRESET = –14.5 V

35

mW

VRESET = –14 V

24

PTOTAL

Supply power dissipation: Total

162.2

219

mW

LPSDR INPUT(7)

VIH(DC)

DC input high voltage(9)

0.7 × VDD

VDD + 0.3

V

VIL(DC)

DC input low voltage(9)

–0.3

0.3 × VDD

V

VIH(AC)

AC input high voltage(9)

0.8 × VDD

VDD + 0.3

V

VIL(AC)

AC input low voltage(9)

–0.3

0.2 × VDD

V

∆VT

Hysteresis ( VT+ – VT– )

Figure 6-12

0.1 × VDD

0.4 × VDD

V

IIL

Low–level input current

VDD = 1.95 V; VI = 0 V

–100

nA

IIH

High–level input current

VDD = 1.95 V; VI = 1.95 V

100

nA

LPSDR OUTPUT(8)

VOH

DC output high voltage

IOH = –2 mA

0.8 × VDD

V

VOL

DC output low voltage

IOL = 2 mA

0.2 × VDD

V

DLP3010LC

DLPS179C – APRIL 2020 – REVISED JULY 2023

www.ti.com

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