The comparator’s upper and lower input thresholds then distinguish between the proper low-potential of 0.4 V

(maximum) driven directly by SDA1 and the buffered output low-level of B.

Figure 7-4 demonstrate the switching behavior of the I2C isolator, ISO1540, between a controller node at SDA1

and a heavy loaded bus at SDA2.

V

OL1

V

IHT1

SDA1

SDA2

SDA2

SDA1

Transmit

Delay

Transmit

Delay

Receive

Delay

V

IHT2

50%

50%

30%

30%

Receive

Delay

Receive

Delay

VCC1

VCC1

VCC2

VCC2

VCC1

VCC1

VCC2

VCC2

Figure 7-4. SDA Channel Timing in Receive and Transmit Directions

7.4.1 Receive Direction (Left Diagram of )

When the I2C bus drives SDA2 low, SDA1 follows after a certain delay in the receive path. The output low is the

buffered output of VOL1 = 0.75 V, which is sufficiently low to be detected by Schmitt-trigger inputs with a minimum

input-low voltage of VIL = 0.9 V at 3 V supply levels.

When SDA2 is released, its voltage potential increases towards VCC2 following the time-constant formed

by RPU2 and Cbus. After the receive delay, SDA1 is released and also rises towards VCC1, following the

time-constant RPU1 × Cnode. Because of the significant lower time-constant, SDA1 may reach VCC1 before

SDA2 reaches VCC2 potential.

7.4.2 Transmit Direction (Right Diagram of )

When a controller drives SDA1 low, SDA2 follows after a certain delay in the transmit direction. When SDA2

turns low it also causes the output of buffer B to turn low but at a higher 0.75 V level. This level cannot be

observed immediately as it is overwritten by the lower low-level of the controller.

However, when the controller releases SDA1, the voltage potential increases and first must pass the upper input

threshold of the comparator, VIHT1, to release SDA2. SDA1 then increases further until it reaches the buffered

output level of VOL1 = 0.75 V, maintained by the receive path. When comparator C turns high, SDA2 is released

after the delay in transmit direction. It takes another receive delay until B’s output turns high and fully releases

SDA1 to move toward VCC1 potential.

7.5 Device Functional Modes

Table 7-2 lists the ISO154x functional modes.

Table 7-2. Function Table

POWER STATE

INPUT

OUTPUT

VCC1 or VCC2 < 2.1 V

X

Z

VCC1 and VCC2 > 2.8 V

L

L

VCC1 and VCC2 > 2.8 V

H

Z

VCC1 and VCC2 > 2.8 V

Z(1)

?

(1)

Invalid input condition as an I2C system requires that a pullup resistor to VCC is connected.

www.ti.com

ISO1540, ISO1541

SLLSEB6F – JULY 2012 – REVISED DECEMBER 2022

Copyright © 2022 Texas Instruments Incorporated

Submit Document Feedback

21

Product Folder Links: ISO1540 ISO1541