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LSF0108 Datasheet(PDF) 142 Page - Nexperia B.V. All rights reserved |
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LSF0108 Datasheet(HTML) 142 Page - Nexperia B.V. All rights reserved |
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142 / 234 page ![]() Schmitt-triggers Type number Description V CC (V) Logic switching levels Output drive capability (mA) t pd (ns) Output Load C L (pF) f max (MHz) Number of bits T amb (°C) 74AHC132 Quad 2-input NAND gate Schmitt-trigger 2.0 - 5.5 CMOS ±8 3.3 50 60 4 -40 to 125 74AHC14 Hex inverter Schmitt-trigger 2.0 - 5.5 CMOS ±8 3.2 50 60 6 -40 to 125 74AHC1G14 Single inverter Schmitt-trigger 2.0 - 5.5 CMOS ±8 3.2 50 60 1 -40 to 125 74AHC1G17 Single buffer Schmitt-trigger 2.0 - 5.5 CMOS ±8 3.2 50 60 1 -40 to 125 74AHC3G14 Triple inverter Schmitt-trigger 2.0 - 5.5 CMOS ±8 3.2 50 60 3 -40 to 125 74AHCT132 Quad 2-input NAND gate Schmitt-trigger; TTL- enabled 4.5 - 5.5 TTL ±8 3.5 50 60 4 -40 to 125 74AHCT14 Hex inverter Schmitt-trigger; TTL-enabled 4.5 - 5.5 TTL ±8 4.0 50 60 6 -40 to 125 74AHCT17A Hex buffer Schmitt-trigger 4.5 - 5.5 TTL ±8 3.2 50 60 8 -40 to 125 74AHCT1G14 Single inverter Schmitt-trigger; TTL-enabled 4.5 - 5.5 TTL ±8 4.1 50 60 1 -40 to 125 74AHCT1G17 Single buffer Schmitt-trigger; TTL-enabled 4.5 - 5.5 TTL ±8 4.1 50 60 1 -40 to 125 74AHCT3G14 Triple inverter Schmitt-trigger; TTL-enabled 4.5 - 5.5 TTL ±8 4.1 50 60 3 -40 to 125 74AHCV05A Hex inverter; Schmitt trigger; open-drain 2.0 - 5.5 CMOS ± 16 5.8 15 10 6 -40 to 125 74AHCV07A Hex buffer Schmitt-trigger; open-drain 1.8 - 5.5 CMOS 16 3.8 15 60 6 -40 to 125 74AHCV14A Hex inverter Schmitt-trigger 1.8 - 5.5 CMOS ±16 3.2 15 60 6 -40 to 125 74AHCV17A Hex buffer Schmitt-trigger 1.8 - 5.5 CMOS ±16 3.2 15 60 6 -40 to 125 74AHCV244A Octal buffer/line driver Schmitt-trigger (3-state) 1.8 - 5.5 CMOS ±16 3.0 15 60 8 -40 to 125 74AHCV245A Octal transceiver Schmitt-trigger (3-state) 1.8 - 5.5 CMOS ±16 3.2 15 60 8 -40 to 125 74AHCV541A Octal buffer/line driver Schmitt-trigger (3-state) 1.8 - 5.5 CMOS ±16 3.0 15 60 8 -40 to 125 74ALVC14 Hex inverter Schmitt-trigger 1.65 - 3.6 TTL ±24 2.4 50 150 6 -40 to 85 74AUP1G132 Single 2-input NAND gate Schmitt-trigger 1.1 - 3.6 CMOS ±1.9 10.0 30 70 1 -40 to 125 74AUP1G14 Single inverter Schmitt-trigger 1.1 - 3.6 CMOS ±1.9 4.7 30 70 1 -40 to 125 74AUP1G17 Single buffer Schmitt-trigger 1.1 - 3.6 CMOS ±1.9 7.8 30 70 1 -40 to 125 74AUP1G57 Configurable gate; Schmitt-trigger 1.1 - 3.6 CMOS ±1.9 8.7 30 70 1 -40 to 125 74AUP1G58 Configurable gate; Schmitt-trigger 1.1 - 3.6 CMOS ±1.9 8.7 30 70 1 -40 to 125 74AUP1G97 Configurable gate; Schmitt-trigger 1.1 - 3.6 CMOS ±1.9 8.7 30 70 1 -40 to 125 74AUP1G98 Configurable gate; Schmitt-trigger 1.1 - 3.6 CMOS ±1.9 8.9 30 70 1 -40 to 125 74AUP2G132 Dual 2-input NAND gate Schmitt-trigger 1.1 - 3.6 CMOS ±1.9 10 30 70 2 -40 to 125 74AUP2G14 Dual inverter Schmitt-trigger 1.1 - 3.6 CMOS ±1.9 4.7 30 70 2 -40 to 125 74AUP2G17 Dual buffer Schmitt-trigger 1.1 - 3.6 CMOS ±1.9 7.8 30 70 2 -40 to 125 74AUP2G58 Dual configurable gate; Schmitt-trigger 1.1 - 3.6 CMOS ±1.9 8.7 30 70 2 -40 to 125 74AUP2G97 Dual configurable gate; Schmitt-trigger 1.1 - 3.6 CMOS ±1.9 8.7 30 70 2 -40 to 125 Asynchronous interface analog & logic ICs Types in bold represent new products Nexperia selection guide 2020 142 |
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