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LSF0108 Datasheet(PDF) 156 Page - Nexperia B.V. All rights reserved

Part # LSF0108
Description  Discrete and MOSFET components, analog & logic ICs
PDF  234 Pages
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Manufacturer  NEXPERIA [Nexperia B.V. All rights reserved]
Direct Link  https://www.nexperia.com/
Logo NEXPERIA - Nexperia B.V. All rights reserved

LSF0108 Datasheet(HTML) 156 Page - Nexperia B.V. All rights reserved

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Flip-flops
Type number
Description
V
CC
(V)
Logic
switching
levels
Output drive
capability
(mA)
t
pd (ns)
Output
Load C
L
(pF)
f
max
(MHz)
T
amb (°C)
74AHC1G79
Single D-type flip-flop; positive-edge trigger
2.0 - 5.5
CMOS
±8
3.5
50
90
-40 to 125
74AHC273
Octal D-type flip-flop with reset; positive-edge trigger
2.0 - 5.5
CMOS
±8
4.2
50
165
-40 to 125
74AHC374
Octal D-type flip-flop; positive-edge trigger (3-state)
2.0 - 5.5
CMOS
±8
4.4
50
185
-40 to 125
74AHC377
Octal D-type flip-flop with data enable; positive-edge
trigger
2.0 - 5.5
CMOS
±8
3.9
50
175
-40 to 125
74AHC574
Octal D-type flip-flop; positive-edge trigger (3-state)
2.0 - 5.5
CMOS
±8
4.4
50
130
-40 to 125
74AHC74
Dual D-type flip-flop with set and reset; positive-edge
trigger
2.0 - 5.5
CMOS
±8
3.7
50
170
-40 to 125
74AHCT1G79
Single D-type flip-flop; positive-edge trigger; TTL-enabled
4.5 - 5.5
TTL
±8
3.5
50
90
-40 to 125
74AHCT273
Octal D-type flip-flop with reset; positive-edge trigger;
TTL-enabled
4.5 - 5.5
TTL
±8
4.0
50
120
-40 to 125
74AHCT374
Octal D-type flip-flop; positive-edge trigger (3-state)
4.5 - 5.5
TTL
±8
4.3
50
140
-40 to 125
74AHCT377
Octal D-type flip-flop with data enable; positive-edge
trigger; TTL-enabled
4.5 - 5.5
TTL
±8
4.0
50
140
-40 to 125
74AHCT574
Octal D-type flip-flop; positive-edge trigger; TTL-enabled
(3-state)
4.5 - 5.5
TTL
±8
4.4
50
130
-40 to 125
74AHCT74
Dual D-type flip-flop with set and reset; positive-edge
trigger; TTL-enabled
4.5 - 5.5
TTL
±8
3.3
50
160
-40 to 125
74ALVC374
Octal D-type flip-flop; positive-edge trigger (3-state)
1.65 - 3.6
TTL
±24
2.5
50
300
-40 to 85
74ALVC574
Octal D-type flip-flop; positive-edge trigger (3-state)
1.65 - 3.6
TTL
±24
2.5
50
300
-40 to 85
74ALVC74
Dual D-type flip-flop with set and reset; positive-edge
trigger
1.65 - 3.6
TTL
±24
2.3
50
425
-40 to 85
74ALVCH16374
16-bit D-type flip-flop with bus hold; positive-edge trigger
(3-state)
1.2 - 3.6
TTL
±24
2.3
50
350
-40 to 85
74ALVCH16821
20-bit D-type flip-flop; positive-edge trigger (3-state)
2.3 - 3.6
TTL
±24
2.5
50
350
-40 to 85
74ALVCH16823
18-bit D-type flip-flop with bus hold; positive-edge trigger
(3-state)
1.2 - 3.6
TTL
±24
2.1
50
350
-40 to 85
74ALVT162821
20-bit D-type flip-flop; positive-edge trigger (3-state)
2.3 - 3.6
TTL
±12
3.2
50
150
-40 to 85
74ALVT162823
18-bit buffer/line driver with bus hold and 30 Ω
termination resistors (3-state)
2.3 - 3.6
TTL
±12
3.0
50
150
-40 to 85
74ALVT16821
20-bit D-type flip-flop; positive-edge trigger (3-state)
2.3 - 3.6
TTL
-32 / 64
1.8
50
150
-40 to 85
74ALVT16823
18-bit D-type flip-flop with bus hold; positive-edge trigger
(3-state)
2.3 - 3.6
TTL
-32 / 64
1.9
50
250
-40 to 85
74AUP1G175
Single D flip-flop with reset; positive-edge trigger
1.1 - 3.6
CMOS
±1.9
7.4
30
70
-40 to 125
74AUP1G374
Single D-type flip-flop; positive-edge trigger (3-state)
1.1 - 3.6
CMOS
±1.9
7.9
30
400
-40 to 125
74AUP1G74
Single D-type flip-flop with set and reset; positive-edge
trigger
1.1 - 3.6
CMOS
±1.9
9.2
30
400
-40 to 125
74AUP1G79
Single D-type flip-flop; positive-edge trigger
1.1 - 3.6
CMOS
±1.9
9.1
30
400
-40 to 125
74AUP1G80
Single D-type flip-flop; positive-edge trigger
1.1 - 3.6
CMOS
±1.9
9.1
30
400
-40 to 125
74AUP2G79
Dual D-type flip-flop; positive-edge trigger
1.1 - 3.6
CMOS
±1.9
8.5
30
400
-40 to 125
74AUP2G80
Dual D-type flip-flop; positive-edge trigger
1.1 - 3.6
CMOS
±1.9
9.1
30
400
-40 to 125
74AVC16374
16-bit D-type flip-flop; positive-edge trigger (3-state)
1.2 - 3.6
CMOS
±12
1.5
30
350
-40 to 85
74HC107
Dual JK-type flip-flop with reset; negative-edge trigger
2.0 - 6.0
CMOS
±5.2
16
50
78
-40 to 125
74HC109
Dual JK-type flip-flop with set and reset;
positive-edge trigger
2.0 - 6.0
CMOS
±5.2
15
50
75
-40 to 125
74HC112
Dual JK-type flip-flop with set and reset;
negative-edge trigger
2.0 - 6.0
CMOS
±5.2
15
50
66
-40 to 125
74HC173
Quad D-type flip-flop; positive-edge trigger (3-state)
2.0 - 6.0
CMOS
±7.8
17
50
88
-40 to 125
74HC174
Hex D-type flip-flop with reset; positive-edge trigger
2.0 - 6.0
CMOS
±5.2
17
50
99
-40 to 125
74HC175
Quad D-type flip-flop with reset; positive-edge trigger
2.0 - 6.0
CMOS
±5.2
17
50
83
-40 to 125
74HC273
Octal D-type flip-flop with reset; positive-edge trigger
2.0 - 6.0
CMOS
±5.2
15
50
122
-40 to 125
Synchronous interface analog & logic ICs
Nexperia selection guide 2020
156



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