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LSF0108 Datasheet(PDF) 157 Page - Nexperia B.V. All rights reserved

Part # LSF0108
Description  Discrete and MOSFET components, analog & logic ICs
PDF  234 Pages
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Manufacturer  NEXPERIA [Nexperia B.V. All rights reserved]
Direct Link  https://www.nexperia.com/
Logo NEXPERIA - Nexperia B.V. All rights reserved

LSF0108 Datasheet(HTML) 157 Page - Nexperia B.V. All rights reserved

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background image
Type number
Description
V
CC
(V)
Logic
switching
levels
Output drive
capability
(mA)
t
pd (ns)
Output
Load C
L
(pF)
f
max
(MHz)
T
amb (°C)
74HC374
Octal D-type flip-flop; positive-edge trigger (3-state)
2.0 - 6.0
CMOS
±7.8
14
50
83
-40 to 125
74HC377
Octal D-type flip-flop with data enable;
positive-edge trigger
2.0 - 6.0
CMOS
±7.8
13
50
83
-40 to 125
74HC574
Octal D-type flip-flop; positive-edge trigger (3-state)
2.0 - 6.0
CMOS
±7.8
14
50
133
-40 to 125
74HC73
Dual JK-type flip-flop with reset; negative-edge trigger
2.0 - 6.0
CMOS
±5.2
16
50
77
-40 to 125
74HC74
Dual D-type flip-flop with set and reset;
positive-edge trigger
2.0 - 6.0
CMOS
±5.2
14
50
82
-40 to 125
74HCT107
Dual JK-type flip-flop with reset;
negative-edge trigger; TTL-enabled
4.5 - 5.5
TTL
±4
16
50
73
-40 to 125
74HCT109
Dual JK-type flip-flop with set and reset;
positive-edge trigger; TTL-enabled
4.5 - 5.5
TTL
±4
17
50
61
-40 to 125
74HCT112
Dual JK-type flip-flop with set and reset;
negative-edge trigger; TTL-enabled
4.5 - 5.5
TTL
±4
19
50
70
-40 to 125
74HCT173
Quad D-type flip-flop; positive-edge trigger;
TTL-enabled (3-state)
4.5 - 5.5
TTL
±6
17
50
88
-40 to 125
74HCT174
Hex D-type flip-flop with reset; positive-edge trigger;
TTL-enabled
4.5 - 5.5
TTL
±4
18
50
69
-40 to 125
74HCT175
Quad D-type flip-flop with reset; positive-edge trigger;
TTL-enabled
4.5 - 5.5
TTL
±4
16
50
54
-40 to 125
74HCT273
Octal D-type flip-flop with reset; positive-edge trigger;
TTL-enabled
4.5 - 5.5
TTL
±4
15
50
36
-40 to 125
74HCT374
Octal D-type flip-flop; positive-edge trigger;
TTL-enabled (3-state)
4.5 - 5.5
TTL
±6
13
50
48
-40 to 125
74HCT377
Octal D-type flip-flop with data enable;
positive-edge trigger; TTL-enabled
4.5 - 5.5
TTL
±6
14
50
53
-40 to 125
74HCT574
Octal D-type flip-flop; positive-edge trigger;
TTL-enabled (3-state)
4.5 - 5.5
TTL
±6
15
50
76
-40 to 125
74HCT74
Dual D-type flip-flop with set and reset;
positive-edge trigger; TTL-enabled
4.5 - 5.5
TTL
±4
15
50
59
-40 to 125
74LV74
Dual D-type flip-flop with set and reset;
positive-edge trigger
1.0 - 5.5
TTL
±12
11
50
75
-40 to 125
74LVC16374A
16-bit D-type flip-flop; positive-edge trigger (3-state)
1.2 - 3.6
CMOS/ LVTTL
±24
3.8
50
150
-40 to 125
74LVC1G175
Single D flip-flop with reset;
positive-edge trigger
1.65 - 5.5
CMOS/ LVTTL
±32
3.1
50
300
-40 to 125
74LVC1G74
Single D-type flip-flop with set and reset;
positive-edge trigger
1.65 - 5.5
CMOS/ LVTTL
±32
3.5
50
280
-40 to 125
74LVC1G79
Single D-type flip-flop;
positive-edge trigger
1.65 - 5.5
CMOS/ LVTTL
±32
2.2
50
450
-40 to 125
74LVC1G80
Single D-type flip-flop;
positive-edge trigger
1.65 - 5.5
CMOS/ LVTTL
±32
2.4
50
450
-40 to 125
74LVC273
Octal D-type flip-flop with reset;
positive-edge trigger
1.2 - 3.6
CMOS/ LVTTL
±24
6.0
50
230
-40 to 125
74LVC2G74
Single D-type flip-flop with set and reset;
positive-edge trigger
1.65 - 5.5
CMOS/ LVTTL
±32
3.5
50
280
-40 to 125
74LVC374A
Octal D-type flip-flop;
positive-edge trigger (3-state)
1.2 - 3.6
CMOS/ LVTTL
±24
2.7
50
100
-40 to 125
74LVC377
Octal D-type flip-flop with data enable;
positive-edge trigger
1.2 - 3.6
CMOS/ LVTTL
±24
6.0
50
230
-40 to 125
74LVC574A
Octal D-type flip-flop;
positive-edge trigger (3-state)
1.2 - 3.6
CMOS/ LVTTL
±24
3.2
50
150
-40 to 125
74LVC74A
Dual D-type flip-flop with set and reset;
positive-edge trigger
1.2 - 3.6
CMOS/ LVTTL
±24
2.5
50
250
-40 to 125
74LVC823A
9-bit D-type flip-flop; positive-edge trigger (3-state)
1.2 - 3.6
CMOS/ LVTTL
±24
5.4
50
150
-40 to 125
74LVCH162374A
16-bit D-type flip-flop with bus hold and 30 Ω termination
resistors; positive-edge trigger (3-state)
1.2 - 3.6
CMOS/ LVTTL
±24
3.8
50
150
-40 to 125
74LVCH16374A
16-bit D-type flip-flop with bus hold;
positive-edge trigger (3-state)
1.2 - 3.6
CMOS/ LVTTL
±24
3.8
50
150
-40 to 125
74LVT162374
16-bit D-type flip-flop with bus hold and 30 Ω termination
resistors; positive-edge trigger (3-state)
2.7 - 3.6
TTL
±12
3.0
50
150
-40 to 85
74LVT16374A
16-bit D-type flip-flop with bus hold; positive-edge trigger
(3-state)
2.7 - 3.6
TTL
-32 / 64
3.0
50
150
-40 to 85
74LVTH16374A
16-bit D-type flip-flop with bus hold; positive-edge trigger
(3-state)
2.7 - 3.6
TTL
-32 / 64
3.0
50
150
-40 to 85
HEF4013B
Dual D-type flip-flop with set and reset; positive-edge
trigger
3.0 - 15.0
CMOS
±2.4
30
50
40
-40 to 85
HEF40175B
Quad D-type flip-flop with reset; positive-edge trigger
3.0 - 15.0
CMOS
±2.4
25
50
45
-40 to 85
HEF4027B
Dual JK-type flip-flop
3.0 - 15.0
CMOS
±2.4
30
50
30
-40 to 85
Flip-Flops
Synchronous interface analog & logic ICs
157



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