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LSF0108 Datasheet(PDF) 161 Page - Nexperia B.V. All rights reserved

Part # LSF0108
Description  Discrete and MOSFET components, analog & logic ICs
PDF  234 Pages
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Manufacturer  NEXPERIA [Nexperia B.V. All rights reserved]
Direct Link  https://www.nexperia.com/
Logo NEXPERIA - Nexperia B.V. All rights reserved

LSF0108 Datasheet(HTML) 161 Page - Nexperia B.V. All rights reserved

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Control analog & logic ICs
Combination Gates
Configurable Gates
Type number
Description
V
CC (V)
Logic
switching
levels
Output drive
capability
(mA)
t
pd (ns)
Output Load
C
L (typ) (pF)
f
max
(MHz)
Number
of bits
T
amb (°C)
74AUP1G0832
Single 3-input AND-OR gate
1.1 - 3.6
CMOS
±1.9
6.7
30
70
1
-40 to 125
74AUP1G3208
Single 3-input OR-AND gate
1.1 - 3.6
CMOS
±1.9
7.4
30
70
1
-40 to 125
74AUP1G885
Dual function gate
1.1 - 3.6
CMOS
±1.9
7.6
30
70
1
-40 to 125
74AUP1Z04
Crystal driver with enable and internal resistor
1.1 - 3.6
CMOS
±1.9
5.6
30
70
1
-40 to 125
74AUP1Z125
Crystal driver with enable and internal resistor
(3-state)
1.1 - 3.6
CMOS
±1.9
4.7
30
70
1
-40 to 125
74AUP2G0604
Inverter with open drain and inverter
1.1 - 3.6
CMOS
±1.9
4.0
30
70
2
-40 to 125
74AUP2G3404
Buffer and inverter
1.1 - 3.6
CMOS
±1.9
4.0
30
70
2
-40 to 125
74AUP2G3407
Buffer and buffer with open drain
1.1 - 3.6
CMOS
±1.9
4.1
30
70
2
-40 to 125
74AUP3G0434
Dual inverter and single buffer
1.1 - 3.6
CMOS
±1.9
4.0
30
70
3
-40 to 125
74AUP3G3404
Dual buffer and single inverter
1.1 - 3.6
CMOS
±1.9
4.0
30
70
3
-40 to 125
74LVC1GX04
Crystal driver
1.65 - 5.5
CMOS /
LVTTL
±24
2.8
50
150
1
-40 to 125
HEF4007UB
Dual complementary paIR and inverter
3.0 - 15
CMOS
±3.4
15
50
10
2
-40 to 85
Type number
Description
V
CC (V)
Logic
switching
levels
Output drive
capability
(mA)
t
pd (ns)
Output Load
C
L (typ) (pF)
f
max
(MHz)
Number
of bits
T
amb (°C)
74AUP1G57
Configurable gate; Schmitt-trigger
1.1 - 3.6
CMOS
±1.9
8.7
30
70
1
-40 to 125
74AUP1G58
Configurable gate; Schmitt-trigger
1.1 - 3.6
CMOS
±1.9
8.7
30
70
1
-40 to 125
74AUP1G97
Configurable gate; Schmitt-trigger
1.1 - 3.6
CMOS
±1.9
8.7
30
70
1
-40 to 125
74AUP1G98
Configurable gate; Schmitt-trigger
1.1 - 3.6
CMOS
±1.9
8.9
30
70
1
-40 to 125
74AUP1G3208
Configurable multiple function gate
0.8 - 3.6
CMOS
±4
6.6
30
70
1
-40 to 125
74AUP1T57
Configurable gate with voltage-level translation
2.3 - 3.6
CMOS
±4
3.8
15
70
1
-40 to 125
74AUP1T58
Configurable gate with voltage-level translation
2.3 - 3.6
CMOS
±4
3.8
15
70
1
-40 to 125
74AUP1T97
Configurable gate with voltage-level translation
2.3 - 3.6
CMOS
±4
3.8
15
70
1
-40 to 125
74AUP1T98
Configurable gate with voltage-level translation
2.3 - 3.6
CMOS
±4
3.8
15
70
1
-40 to 125
74AUP2G57
Dual configurable gate; Schmitt-trigger
0.8 - 3.6
CMOS
±4
6.6
30
70
1
-40 to 125
74AUP2G58
Dual configurable gate; Schmitt-trigger
0.8 - 3.6
CMOS
±4
6.6
30
70
1
-40 to 125
74AUP2G97
Dual configurable gate; Schmitt-trigger
0.8 - 3.6
CMOS
±4
6.6
30
70
1
-40 to 125
74AUP2G98
Dual configurable gate; Schmitt-trigger
0.8 - 3.6
CMOS
±4
6.6
30
70
1
-40 to 125
74AXP1G57
Configurable gate; Schmitt-trigger
0.7 - 2.75
CMOS
±4.5
4.6
5
70
1
-40 to 85
74AXP1G58
Configurable gate; Schmitt-trigger
0.7 - 2.75
CMOS
±4.5
4.5
5
70
1
-40 to 85
74AXP1G97
Configurable gate; Schmitt-trigger
0.7 - 2.75
CMOS
±4.5
4.5
5
70
1
-40 to 85
74AXP1G98
Configurable gate; Schmitt-trigger
0.7 - 2.75
CMOS
±4.5
4.5
5
70
1
-40 to 85
74LVC1G57
Configurable gate; Schmitt-trigger
1.65 - 5.5
CMOS/
LVTTL
±32
6.3
50
150
1
-40 to 125
74LVC1G58
Configurable gate; Schmitt-trigger
1.65 - 5.5
CMOS/
LVTTL
±32
6.3
50
150
1
-40 to 125
74LVC1G97
Configurable gate; Schmitt-trigger
1.65 - 5.5
CMOS/
LVTTL
±32
6.3
50
150
1
-40 to 125
74LVC1G98
Configurable gate; Schmitt-trigger
1.65 - 5.5
CMOS/
LVTTL
±32
6.3
50
150
1
-40 to 125
74LVC1G99
Configurable gate; Schmitt-trigger
1.65 - 5.5
CMOS/
LVTTL
±32
8.4
50
150
1
-40 to 125
161



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