LMC567

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SNOSBY1C – JUNE 1999 – REVISED DECEMBER 2015

Feature Description (continued)

9.3.2 Input

The input pin 3 is internally ground-referenced with a nominal 40-k

Ω resistor. Signals which are already centered

on 0 V may be directly coupled to pin 3; however, any DC potential must be isolated through a coupling

capacitor. Inputs of multiple LMC567 devices can be paralleled without individual DC isolation.

9.3.3 Loop Filter

Pin 2 is the combined output of the phase detector and control input of the VCO for the phase-locked loop (PLL).

Capacitor C2 in conjunction with the nominal 80-k

Ω pin 2 internal resistance forms the loop filter.

For small values of C2, the PLL has a fast acquisition time and the pull-in range is set by the built in VCO

frequency stops, which also determines the largest detection bandwidth (LDBW). Increasing C2 results in

improved noise immunity at the expense of acquisition time, and the pull-in range begins to become narrower

than the LDBW (see Figure 4). However, the maximum hold-in range always equal the LDBW.

9.3.4 Output Filter

Pin 1 is the output of a negative-going amplitude detector which has a nominal 0 signal output of 7/9 Vs. When

the PLL is locked to the input, an increase in signal level causes the detector output to move negative. When pin

1 reaches 2/3 Vs, the output is activated (see Output).

Capacitor C1 in conjunction with the nominal 40-k

Ω pin 1 internal resistance forms the output filter. The size of

C1 is a tradeoff between slew rate and carrier ripple at the output comparator. Low values of C1 produce the

least delay between the input and output for tone burst applications, while larger values of C1 improve noise

immunity.

Pin 1 also provides a means for shifting the input threshold higher or lower by connecting an external resistor to

supply or ground. However, reducing the threshold using this technique increases sensitivity to pin 1 carrier

ripple and also results in more part to part threshold variation.

9.3.5 Output

The output at pin 8 is an N-channel FET switch to ground which is activated when the PLL is locked and the

input tone is of sufficient amplitude to cause pin 1 to fall below 2/3 Vs. Apart from the obvious current component

due to the external pin 8 load resistor, no additional supply current is required to activate the switch. The ON-

resistance of the switch is inversely proportional to supply; thus the sat voltage for a given output current

increases at lower supplies.

9.4 Device Functional Modes

9.4.1 Operation as LM567

The LMC567 low power tone decoder can be operated at supply voltages of 2 V to 9 V and at input frequencies

ranging from 1 Hz up to 500 kHz.

The LMC567 can be directly substituted in most LM567 applications with the following provisions:

1. Oscillator timing capacitor Ct must be halved to double the oscillator frequency relative to the input frequency

(see Oscillator).

2. Filter capacitors C1 and C2 must be reduced by a factor of 8 to maintain the same filter time constants.

3. The output current demanded of pin 8 must be limited to the specified capability of the LMC567.

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