LP3995

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SNVS179F – FEBRUARY 2003 – REVISED SEPTEMBER 2015

9.2.2.6 Noise Bypass Capacitor

A bypass capacitor should be connected between the BYPASS pin and ground to significantly reduce the noise

at the regulator output. This device pin connects directly to a high impedance node within the bandgap reference

circuitry. Any significant loading on this node causes a change on the regulated output voltage. For this reason,

DC leakage current through this pin must be kept as low as possible for best output voltage accuracy.

The use of a 0.01-µF bypass capacitor is strongly recommended to prevent overshoot on the output during start-

up.

The types of capacitors best suited for the noise bypass capacitor are ceramic and film. High quality ceramic

capacitors with NPO or COG dielectric typically have very low leakage. Polypropolene and polycarbonate film

capacitors are available in small surface-mount packages and typically have extremely low leakage current.

Unlike many other LDOs, the addition of a noise reduction capacitor does not effect the transient response of the

device.

9.2.2.7 Fast Turnoff and Turnon

The controlled switch-off feature of the device provides a fast turn off by discharging the output capacitor via an

internal FET device. This discharge is current limited by the RDSon of this switch. Fast turnon is ensured by

control circuitry within the reference block allowing a very fast ramp of the output voltage to reach the target

voltage.

9.2.2.8 Power Dissipation

The permissible power dissipation for any package is a measure of the capability of the device to pass heat from

the power source, the junctions of the device, to the ultimate heat sink, the ambient environment. Thus the power

dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces

between the die and ambient air.

Equation 1 restates the equation given in note 5 of Absolute Maximum Ratings:

TA(MAX) = TJ(MAX-OP) − (PD(MAX) × RθJA)

(1)

The allowable power dissipation for the device in a given package can be calculated:

PD = TJ(MAX) – TA / RθJA

(2)

With an RθJA = 255°C/W, the device in the DSBGA package returns a value of 392 mW with a maximum junction

temperature of 125°C.

With an RθJA = 88°C/W, the device in the WSON package returns a value of 1.136 mW with a maximum junction

temperature of 125°C.

The actual power dissipation across the device can be represented by Equation 3:

PD = (VIN − VOUT) × IOUT

(3)

This establishes the relationship between the power dissipation allowed due to thermal consideration, the voltage

drop across the device, and the continuous current capability of the device. Equation 2 and Equation 3 should be

used to determine the optimum operating conditions for the device in the application.

This thermal resistance (RθJA) is highly dependent on the heat-spreading capability of the particular PCB design,

and therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA

recorded in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and

copper-spreading area and is to be used only as a relative measure of package thermal performance. For a well-

designed thermal layout, RθJA is actually the sum of the package junction-to-case (bottom) thermal resistance

(RθJCbot) plus the thermal resistance contribution by the PCB copper area acting as a heatsink.

9.2.2.9 Estimating Junction Temperature

The EIA/JEDEC standard recommends the use of psi (

Ψ) thermal characteristics to estimate the junction

temperatures of surface mount devices on a typical PCB board application. These characteristics are not true

thermal resistance values, but rather package specific thermal characteristics that offer practical and relative

means of estimating junction temperatures. These psi metrics are determined to be significantly independent of

copper-spreading area. The key thermal characteristics (

ΨJT and ΨJB) are given in Thermal Information and are

used in accordance with Equation 4 or Equation 5.

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