SNR(dBc)=-20xLOG10(2x

xf

xj

)

p

IN

TOTAL

(1)

j

=(j

+j

)

TOTAL

ADC

CLOCK

2

1/2

2

(2)

ADS5463

ADS54RF63

SLAS515E – NOVEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com

Table 2. Recommended RMS Clock Jitter

INPUT FREQUENCY

MEASURED SNR

TOTAL JITTER

MAXIMUM CLOCK JITTER

(MHz)

(dBc)

(fsec rms)

(fsec rms)

10

64.4

9590

9589

70

64.4

1370

1362

100

64.3

970

959

230

64.1

432

405

300

64

335

300

450

63.6

234

181

650

62.9

175

94

1300

58.3

149

16

Equation 1 and Equation 2 are used to estimate the required clock source jitter.

where:

jTOTAL = the rms summation of the clock and ADC aperture jitter;

jADC = the ADC internal aperture jitter which is located in the data sheet;

jCLOCK = the rms jitter of the clock at the clock input pins to the ADC; and

fIN = the analog input frequency.

Notice that the SNR is a strong function of the analog input frequency, not the clock frequency. The slope of the

clock source edges can have a mild impact on SNR as well and is not taken into account for these estimates.

For this reason, maximizing clock source amplitudes at the ADC clock inputs is recommended, though not

required (faster slope is desirable for jitter-related SNR). For more information on clocking high-speed ADCs, see

application note SLWA034, Implementing a CDC7005 Low Jitter Clock Solution For High-Speed, High-IF ADC

Devices. Recommended clock distribution chips (CDCs) are the TI CDC7005, the CDCM7005, and the

CDCE72010. Depending on the jitter requirements, a band pass filter (BPF) is sometimes required between the

CDC and the ADC. If the insertion loss of the BPF causes the clock amplitude to be too low for the ADC, or the

clock source amplitude is too low to begin with, an inexpensive amplifier can be placed between the CDC and

the BPF.

Figure 65 represents a scenario where an LVCMOS single-ended clock output is used from a TI CDCM7005 with

the clock signal path optimized for maximum amplitude and minimum jitter. This type of conditioning might

generally be well-suited for use with greater than 250 MHz of input frequency. The jitter of this setup is difficult to

estimate and requires a careful phase noise analysis of the clock path. The BPF (and possibly a low-cost

amplifier because of insertion loss in the BPF) can improve the jitter between the CDC and ADC when the jitter

provided by the CDC is still not adequate. The total jitter at the CDCM7005 output depends largely on the phase

noise of the VCXO selected, as well as the CDCM7005, and typically has 50 fs – 100 fs of rms jitter. If it is

determined that the jitter from the CDCM7005 with a VCXO is sufficient without further conditioning, it is possible

to clock the ADS5463/ADS54RF63 directly from the CDCM7005 using differential LVPECL outputs, as illustrated

in Figure 66 (see the CDCM7005 data sheet for the exact schematic). This scenario may be more suitable for

less than 150 MHz of input frequency where jitter is not as critical. A careful analysis of the required jitter and of

the components involved is recommended before determining the proper approach.

34

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