Low-JitterClockDistribution

500MHz

BPF

XFMR

AMP

AMP and/orBPFareOptional

ThisisanExampleBlockDiagram.

ADC

ADS5463

VCO

REF

CDC

(ClockDistributionChip)

CDCM7005

1000MHz(to TransmitDAC)

125MHz(toDSP)

250MHz(toFPGA)

ToOther

BoardMaster

ReferenceClock

(HighorLowJitter)

10MHz

Low-JitterOscillator

1000MHz

LVCMOS

LVPECL

or

LVCMOS

CLKIN

CLKIN

.

.

.

B0268-03

ThisisanExampleBlockDiagram.

Low-JitterClockDistribution

ADC

ADS5463

VCO

REF

CDC

(ClockDistributionChip)

CDCM7005

1000MHz(to TransmitDAC)

125MHz(toDSP)

250MHz(toFPGA)

ToOther

BoardMaster

ReferenceClock

(HighorLowJitter)

10MHz

500MHz

Low-JitterOscillator

1000MHz

LVPECL

LVPECL

or

LVCMOS

CLKIN

CLKIN

.

.

.

B0343-01

ADS5463

ADS54RF63

www.ti.com ................................................................................................................................................... SLAS515E – NOVEMBER 2006 – REVISED JULY 2009

Consult the CDCM7005 data sheet for proper schematic and specifications regarding allowable input and output

frequency and amplitude ranges.

Figure 65. Optimum Jitter Clock Circuit

Consult the CDCM7005 data sheet for proper schematic and specifications regarding allowable input and output

frequency and amplitude ranges.

Figure 66. Acceptable Jitter Clock Circuit

Copyright © 2006–2009, Texas Instruments Incorporated

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