Digital Outputs

ADS5463

ADS54RF63

SLAS515E – NOVEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com

The ADC provides 12 LVDS-compatible, offset binary data outputs (D11 to D0; D11 is the MSB and D0 is the

LSB), a data-ready signal (DRY), and an over-range indicator (OVR). It is recommended to use the DRY signal

to capture the output data of the ADS5463/ADS54RF63. DRY is source-synchronous to the DATA/OVR outputs

and operates at the same frequency, creating a half-rate DDR interface that updates data on both the rising and

falling edges of DRY. It is recommended that the capacitive loading on the digital outputs be minimized. Higher

capacitance shortens the data-valid timing window. The values given for timing (see Figure 1) were obtained with

a measured 10-pF parasitic board capacitance to ground on each LVDS line (or 5-pF differential parasitic

capacitance). When setting the time relationship between DRY and DATA at the receiving device, it is generally

recommended that setup time be maximized, but this partially depends on the setup and hold times of the device

receiving the digital data (like an FPGA, Field Programmable Gate Array). Since DRY and DATA are coincident,

it will likely be necessary to delay either DRY or DATA such that setup time is maximized.

Referencing Figure 1, the polarity of DRY with respect to the sample N data output transition is undetermined

because of the unknown startup logic level of the clock divider that generates the DRY signal (DRY is a

frequency divide-by-two of CLK). Either the rising or the falling edge of DRY will be coincident with sample N and

the polarity of DRY could invert when power is cycled off/on. Data capture from the transition and not the polarity

of DRY is recommended, but not required. If the synchronization of multiple ADS5463/ADS54RF63 devices is

required, it might be necessary to use a form of the CLKIN signal rather than DRY to capture the data. Studying

the timing characteristics, it can be seen that the ADS54RF63 offers more tightly controlled timing parameters

than the ADS5463. Depending on the setup/hold requirements of the FPGA in use, it may be possible to use the

DRY from a single ADS54RF63 to latch data into the FPGA from multiple ADS54RF63. This would prove much

more difficult with the ADS5463 at full clock speed due to more restrictive timing parameters.

The DRY frequency is identical on the ADS5463/ADS54RF63 to the ADS5474 (where DRY equals half of the

CLK frequency), but different to the pin-similar ADS5444/ADS5440 (where DRY equals the CLK frequency). The

LVDS outputs all require an external 100-

Ω load between each output pair in order to meet the expected LVDS

voltage levels. For long trace lengths, it may be necessary to place a 100-

Ω load on each digital output as close

to the ADC as possible and another 100-

Ω differential load at the end of the LVDS transmission line to provide

matched impedance and avoid signal reflections. The effective load in this case reduces the LVDS voltage levels

by half.

The OVR output equals a logic high when the 12-bit output word attempts to exceed either all 0s or all 1s. The

digital outputs will clip to all 0s or all 1s if the input is out of range. The OVR signal is provided as an indicator

that the analog input signal exceeded the full-scale input limit of approximately 2.2 VPP (± gain error). The OVR

indicator is provided for systems that use gain control to keep the analog input signal within acceptable limits.

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