ADS8568 datasheet(28/62 Pages) TI2

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SOURCE

ACQ

C ln(2)(n+1)

- (R

+R )

SER

3dB

ln(2)(n+1)

2 t

ACQ

ADS8528, ADS8548, ADS8568

SBAS543C – AUGUST 2011 – REVISED FEBRUARY 2016

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9.3 Feature Description

9.3.1 Analog

This section addresses the analog input circuit, the ADCs and control signals, and the reference design of the

device.

9.3.1.1 Analog Inputs

The inputs and the converters are of single-ended bipolar type. The absolute voltage range can be selected

using the RANGE pin (in hardware mode) or RANGE_x bits (in software mode) in the Configuration (CONFIG)

CONFIG register), the input voltage range can be ±10 V or ±5 V. With the internal reference source set to 3 V

(CONFIG bit C13 = 1), an input voltage range of ±12 V or ±6 V can be configured. The logic state of the RANGE

pin is latched with the falling edge of BUSY (if CONFIG bit C26 = 0).

The input current on the analog inputs depends on the actual sample rate, input voltage, and signal source

impedance. Essentially, the current into the analog inputs charges the internal capacitor array only during the

sampling period (tACQ). The source of the analog input voltage must be able to charge the input capacitance of

10 pF in ±4-VREF mode or of 20 pF in ±2-VREF mode to a 12-, 14-, or 16-bit accuracy level within the

acquisition time; see Figure 35. During the conversion period, there is no further input current flow and the input

impedance is greater than 1 MΩ. To ensure a defined start condition, the sampling capacitors of the ADS85x8

are pre-charged to a fixed internal voltage before switching into sampling mode.

To maintain the linearity of the converter, the inputs must always remain within the specified range defined in the

Electrical Characteristics table. The minimum –3-dB bandwidth of the driving operational amplifier can be

calculated using Equation 1:

where

•

n = 12, 14, or 16; n is the resolution of the ADS85x8

(1)

With a minimum acquisition time of tACQ = 280 ns, the required minimum bandwidth of the driving amplifier is 5.2

MHz for the ADS8528, 6.0 MHz for the ADS8548, or 6.7 MHz for the ADS8568. The required bandwidth can be

lower if the application allows a longer acquisition time. A gain error occurs if a given application does not fulfill

the bandwidth requirement shown in Equation 1.

A driving operational amplifier may not be required if the impedance of the signal source (RSOURCE) fulfills the

requirement of Equation 2:

where

•

n = 12, 14, or 16; n is the resolution of the ADC

•

CS = 10 pF is the sample capacitor value in VIN = ±4-VREF mode

•

RSER = 200 Ω is the input resistor value

•

and RSW = 130 Ω is the switch resistance value

(2)

With a minimum acquisition time of tACQ = 280 ns, the maximum source impedance must be less than 2.7 kΩ for

the ADS8528, 2.3 kΩ for the ADS8548, and 2.0 kΩ for the ADS8568 in ±4V-REF mode, or less than 1.2 kΩ for

the ADS8528, 1.0 kΩ for the ADS8548, and 0.8 kΩ for the ADS8568 in ±2-VREF mode. The source impedance

can be higher if the application allows a longer acquisition time.

9.3.1.2 Analog-to-Digital Converter (ADC)

The device includes eight ADCs that operate with either an internal or an external conversion clock.

ADS8568 Datasheet(PDF) 28 Page - Texas Instruments

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