ADS8568 datasheet(8/62 Pages) TI2

8 / 62 page

ADS8528, ADS8548, ADS8568

SBAS543C – AUGUST 2011 – REVISED FEBRUARY 2016

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Product Folder Links: ADS8528 ADS8548 ADS8568

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Pin Functions (continued)

TYPE(1)

DESCRIPTION

NAME

NO.

PARALLEL INTERFACE (PAR/SER = 0)

SERIAL INTERFACE (PAR/SER = 1)

REFAN

Decoupling capacitor input for reference of channel pair A.

Connect to the decoupling capacitor and AGND according to the Power Supply Recommendations section.

REFAP

Decoupling capacitor input for reference of channel pair A.

Connect to the decoupling capacitor according to the Power Supply Recommendations section.

REFBN

Decoupling capacitor input for reference of channel pair B.

Connect to the decoupling capacitor and AGND according to the Power Supply Recommendations section.

REFBP

Decoupling capacitor input for reference of channel pair B.

Connect to the decoupling capacitor according to the Power Supply Recommendations section.

REFCN

Decoupling capacitor input for reference of channel pair C.

Connect to the decoupling capacitor and AGND according to the Power Supply Recommendations section.

REFCP

Decoupling capacitor input for reference of channel pair C.

Connect to the decoupling capacitor according to the Power Supply Recommendations section.

REFDN

Decoupling capacitor input for reference of channel pair D.

Connect to the decoupling capacitor and AGND according to the Power Supply Recommendations section.

REFDP

Decoupling capacitor input for the channel pair D reference.

Connect to the decoupling capacitor according to the Power Supply Recommendations section.

REFEN/WR

DI/DI

Hardware mode (HW/SW = 0): internal

reference enable input.

When high, the internal reference is enabled

(the reference buffers are also enabled).

When low, the internal reference is disabled

and an external reference is applied at

REFIO.

Hardware mode (HW/SW = 0): internal reference enable input.

When high, the internal reference is enabled (the reference buffers

are also enabled).

When low, the internal reference is disabled and an external

reference is applied at REFIO.

Software mode (HW/SW = 1): write input.

The parallel data input is enabled when CS

and WR are low. The internal reference is

enabled by CONFIG bit C15 (REFEN).

Software mode (HW/SW = 1): connect to DGND or DVDD. The

internal reference is enabled by CONFIG bit C15 (REFEN).

REFIO

AIO

Reference voltage input/output.

The internal reference is enabled by the REFEN/WR pin in hardware mode or by CONFIG bit C15 (REFEN) in

software mode. The output value is controlled by the internal digital-to-analog converter (DAC), CONFIG bits

C[9:0]. Connect to a decoupling capacitor according to the Power Supply Recommendations section.

REFN

Negative reference input/output pin.

Connect to a decoupling capacitor and AGND according to the Power Supply Recommendations section.

RESET

Reset input, active high.

This pin aborts any ongoing conversions and resets the internal Configuration register (CONFIG) to 000003FFh.

A valid reset pulse must be at least 50 ns long.

STBY

Hardware mode (HW/SW = 0): standby mode input.

When low, the entire device is powered down (including the internal conversion clock source and reference).

When high, the device operates in normal mode.

Software mode (HW/SW = 1): connect to DGND or DVDD.

The standby mode can be activated using CONFIG bit C25 (STBY).

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