8.2.2.3 Differential to Single-Ended Output Conversion

Figure 8-3 shows an example of a TLV6001-based signal conversion and filter circuit for systems using single-

ended-input ADCs to convert the analog output voltage into digital. With R1 = R2 = R3 = R4, the output voltage

equals (VOUTP – VOUTN) + VREF. Tailor the bandwidth of this filter stage to the bandwidth requirement of the

system. For most applications, R1 = R2 = R3 = R4 = 3.3 kΩ and C1 = C2 = 330 pF yields good performance.

DCDC_OUT

DCDC_HGND

HLDO_IN

HLDO_OUT

HGND

INP

INN

NC

AMC3302

DCDC_IN

LDO_OUT

VDD

OUTP

OUTN

GND

DIAG

DCDC_GND

+

±

R4

R3

R1

R2

VREF

ADC

GND

GND

To MCU

C1

C2

GND

TLV6001

Figure 8-3. Connecting the AMC3302 Output to a Single-Ended Input ADC

For more information on the general procedure to design the filtering and driving stages of successive-

approximation-register (SAR) ADCs, see the 18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest

Distortion and Noise reference guide and 18-Bit Data Acquisition Block (DAQ) Optimized for Lowest Power

reference guide, available for download at www.ti.com.

8.2.3 Application Curve

One important aspect of power-stage design is the effective detection of an overcurrent condition to protect the

switching devices and passive components from damage. To power off the system quickly in the event of an

overcurrent condition, a low delay caused by the isolated amplifier is required. Step Response of the AMC3302

shows the typical fullscale step response of the AMC3302.

VIN

VOUTP

VOUTN

Figure 8-4. Step Response of the AMC3302

AMC3302

SBASA11B – AUGUST 2020 – REVISED JULY 2021

www.ti.com

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