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memory is built-in, which reduces chip-level soft errors and thereby increases reliability. System SRAM is always

initialized to zeroes upon code execution from boot.

To improve code execution speed and lower power when executing code from nonvolatile memory, a 4-way

nonassociative 8 kB cache is enabled by default to cache and prefetch instructions read by the system CPU.

The cache can be used as a general-purpose RAM by enabling this feature in the Customer Configuration Area

(CCFG).

There is a 4 kB ultra-low leakage SRAM available for use with the Sensor Controller Engine which is typically

used for storing Sensor Controller programs, data and configuration parameters. This RAM is also accessible by

the system CPU. The Sensor Controller RAM is not cleared to zeroes between system resets.

The ROM includes a TI-RTOS kernel and low-level drivers, as well as significant parts of selected radio stacks,

which frees up flash memory for the application. The ROM also contains a serial (SPI and UART) bootloader that

can be used for initial programming of the device.

9.5 Sensor Controller

The Sensor Controller contains circuitry that can be selectively enabled in both Standby and Active power

modes. The peripherals in this domain can be controlled by the Sensor Controller Engine, which is a proprietary

power-optimized CPU. This CPU can read and monitor sensors or perform other tasks autonomously; thereby

significantly reducing power consumption and offloading the system CPU.

The Sensor Controller Engine is user programmable with a simple programming language that has syntax

similar to C. This programmability allows for sensor polling and other tasks to be specified as sequential

algorithms rather than static configuration of complex peripheral modules, timers, DMA, register programmable

state machines, or event routing.

The main advantages are:

• Flexibility - data can be read and processed in unlimited manners while still ensuring ultra-low power

• 2 MHz low-power mode enables lowest possible handling of digital sensors

• Dynamic reuse of hardware resources

• 40-bit accumulator supporting multiplication, addition and shift

• Observability and debugging options

Sensor Controller Studio is used to write, test, and debug code for the Sensor Controller. The tool produces

C driver source code, which the System CPU application uses to control and exchange data with the Sensor

Controller. Typical use cases may be (but are not limited to) the following:

• Read analog sensors using integrated ADC or comparators

• Interface digital sensors using GPIOs, SPI, UART, or I2C (UART and I2C are bit-banged)

• Capacitive sensing

• Waveform generation

• Very low-power pulse counting (flow metering)

• Key scan

The peripherals in the Sensor Controller include the following:

• The low-power clocked comparator can be used to wake the system CPU from any state in which the

comparator is active. A configurable internal reference DAC can be used in conjunction with the comparator.

The output of the comparator can also be used to trigger an interrupt or the ADC.

• Capacitive sensing functionality is implemented through the use of a constant current source, a time-to-digital

converter, and a comparator. The continuous time comparator in this block can also be used as a higher-

accuracy alternative to the low-power clocked comparator. The Sensor Controller takes care of baseline

tracking, hysteresis, filtering, and other related functions when these modules are used for capacitive

sensing.

• The ADC is a 12-bit, 200 ksamples/s ADC with eight inputs and a built-in voltage reference. The ADC can be

triggered by many different sources including timers, I/O pins, software, and comparators.

• The analog modules can connect to up to eight different GPIOs

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CC2652R

SWRS207J – JANUARY 2018 – REVISED NOVEMBER 2023

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