DAC8728 datasheet(34/59 Pages) TI2

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OUT

Gain

REF ´

INPUT_CODE

65536

OFFSETDAC_CODE

65536

(Gain

REF

OUT

Gain

REF ´

DAC_DATA_CODE

65536

OFFSETDAC_CODE

65536

(Gain

REF

DAC_DATA_CODE =

INPUT_CODE

(USER_GAIN+2

)

+USER_ZERO

DAC8728

SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009

www.ti.com

If the user-calibration function is not needed, the correction engine can be turned off to speed up the device.

Setting the SCE bit in the Configuration Register to '0' turns off the correction engine. Setting SCE to '1' enables

the correction engine. When SCE = '0' (default), the data are directly transferred to the DAC Data Register. In

this case, writing to the Gain Register or Zero Register updates the Gain and Zero registers but does not start a

math engine calculation. Reading these registers returns the written values.

ANALOG OUTPUTS (VOUT-0 to VOUT-7, with reference to the ground of REF-x)

When the correction engine is off (SCE = '0'):

(1)

SPACE

When the correction engine is on (SCE = '1'):

(2)

SPACE

Where:

Gain = the DAC gain defined by the GAIN bit in the Configuration Register.

INPUT_CODE = the data written into the Input Data Register.

OFFSETDAC_CODE = the data written into the Offset DAC Register.

USER_GAIN = the code of the Gain Register.

USER_ZERO = the code of the Zero Register.

For single-supply operation, the OFFSET-A pin must be connected to the AGND-A pin and the OFFSET-B pin

must be connected to the AGND-B pin. Offset DAC-A and Offset DAC-B are in a power-down state.

For dual-supply operation, the OFFSET-A and OFFSET-B default code for a gain of 6 is 39322 with a ±10 LSB

variation, depending on the linearity of the Offset DACs. The default code for a gain of 4 is 43691 with a ±10 LSB

variation. The default code of OFFSET-A and OFFSET-B are independently factory trimmed for both gains of 6

and 4.

The power-on default value of the Gain Register is 32768, and the default value of the Zero Register is '0'. The

DAC input registers are set to a default value of 0000h.

Note that the maximum output voltage must not be greater than (AVDD – 0.5V) and the minimum output voltage

must not be less than (AVSS + 0.5V); otherwise, the output may be saturated.

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